December 4, 2012
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
November 16, 2012
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
November 16, 2012
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
November 13, 2012
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
October 11, 2012
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
September 6, 2012
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
August 23, 2012
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
May 22, 2012
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
April 25, 2012
Cutting the cabling to simplify the emulation process.
March 21, 2012
Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
