Synopsys experts are now blogging about key issues in formal verification - how to use it, which techniques to apply, and the effort/reward ratio of doing so.
Videos discuss formal verification planning, correct initialisation, writing constraints, developing properties, interpreting results - and knowing when you have done enough.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
Manufacturability, routing, library design and more - it all needs rethinking at 20nm
Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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