Industry Blogs

December 4, 2012

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
November 16, 2012

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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November 16, 2012

3DIC – the advantages and the challenges of vertical integration

The advantages and challenges of 3D IC integration, as we add vertical functional integration options to the traditional planar integration brought by the progress of Moore's Law.
November 13, 2012

Embedded systems are evolving, but where are the tools?


Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.
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October 11, 2012

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm
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September 6, 2012

Getting ready for 20nm

Tackling the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
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August 23, 2012

Verification challenges require surgical precision

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.
May 22, 2012

Making dummy fill smarter

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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April 25, 2012

No more spaghetti

Cutting the cabling to simplify the emulation process.
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March 21, 2012

The return of the ‘custom’ embedded OS

Colin Walls of Mentor Graphics on a significant surprise in UBM’s latest market survey
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