Collaboration on DTCO offers IBM a better way to evaluate combinations of transistor architectures, materials and other process technology innovations using design metrics, before real wafers become available for physical experimentation.
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
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