Design to Silicon

March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
February 16, 2018

SPIE Advanced Lithography 2018 preview: Mentor

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
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February 13, 2017

SPIE Advanced Lithography preview: Mentor Graphics

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
February 1, 2017

Five steps to faster FPGA implementation

Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.
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December 19, 2016

White paper discusses optimising the efficiency of DDR memory subsystems

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
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October 10, 2016

Speeding up AMS design in the age of finFETs

STMicroelectronics, Samsung, GSI Technology and Synopsys talk about the challenges of doing AMS design on finFET processes.
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August 27, 2016

Creating a reference design flow for 10nm processes: video

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
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May 25, 2016

DAC 2016 preview: Mentor Graphics

An overview of the vendor's busy DAC program from panels to technical sessions to a one-to-one with Wally Rhines.
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April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.

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