Conferences

The chip industry faces problems as foundries and the packaging industry compete over 3D technologies. If resolved, it could mean a new dawn in ASIC design.

STMicroelectronics pushes on with FDSOI despite dissolution of ST-Ericcson joint venture that provided the lead customer for the process.

As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.

The paper on the 32nm upgrade to Big Blue's family of server chips also detailed how the company is tackling BTI.

Keynoter Lisa Su spun a whimsical idea to serious intent as AMD looks to promote its model for heterogeneous architectures

3D-IC integration techniques such as the use of TSVs, die stacking and interposers are unlikely to limit performance, according to research from TSMC and IBM

Can planar devices on fully depleted SOI resist the relentless rise of finFETs as the next device architecture of choice for the semiconductor industry? An evening panel at IEDM explored the trade-offs

Semiconductor process options outlined at IEDM by Luc van den Hove of imec as industry faces hard choices and rising costs

Tabula expects to have 22nm FPGAs next year and is trying to recruit IP developers to an 'app store' for data-center hardware.

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?