Research projects to verify methodologies, address third-party integration challenges and add a low-cost interposer-like technology to the 3D-IC family make their mark.
Dr Ron Black also discussed his experiences with the Internet of Things in a lively keynote at the GSA Memory+ Conference in Taipei
Stacked 3D-IC memory-on-logic is on the packaging company's roadmap, but there are still yield hurdles to scale at the MEOL.
DAC to link chip, software and system design to automotive OEMs with a new track covering 21 topics within four themes. Call for abstracts now open.
Packed one-day event has speakers from Cadence, TSMC, Samsung, Amkor, Advantest and more providing a senior level view of making 3D-IC a reality. Registration closes soon.
Formal techniques now underpin static verification approaches to checking clock domain crossings, constraints, reset and initialization states, and more
Cadence Design Systems has issued a call for papers for the European leg of its CDNLive of events for 2014. The deadline for the Silicon Valley event is also looming: the call closes mid-November 2013.
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
The EDA vendor has set a broad agenda across two Silicon Valley events taking place in late October, with registration now open for both.
TSMC 16nm finFET process and efforts to increase p-finFET mobility using germanium to be detailed at December's International Electron Devices Meeting.
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