Conferences

January 20, 2016

Catching complex CDC bugs in large SoCs

A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
January 14, 2016

DesignCon 2016 preview: Mentor Graphics

HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
December 18, 2015

Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon

Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
December 7, 2015

Asymmetric variability issues could impact 7nm processes

Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
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November 12, 2015

DVCon Europe: UVM-SystemC backers ready first draft

But the bridge standard's European backers still need greater support from the big EDA vendors.
October 12, 2015

Mentor’s Wally Rhines on M&A ‘merger mania’

...and why the semiconductor industry hasn't been singularitied down to one MegaSemis Inc even if that's what M&A data suggests.
October 6, 2015

Samsung taps Mentor tools for higher yielding close-loop DFM

Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
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August 6, 2015

Flow exploration key to finFET network processor implementation

Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
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July 30, 2015

10nm flow reveals complexity of finFET design process

Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
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June 24, 2015

Mediatek extends big.LITTLE strategy with ‘tri-cluster’ smartphone CPU

Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
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