A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
But the bridge standard's European backers still need greater support from the big EDA vendors.
...and why the semiconductor industry hasn't been singularitied down to one MegaSemis Inc even if that's what M&A data suggests.
Samsung bases PRISM and FLARE defect analysis and optimization on Mentor Graphics' Calibre and Tessent. Yields rise. Ramps shorten.
Flow exploration helps designers establish best approach to advanced network processor implementation on Samsung finFET process
Collaboration between ARM, TSMC and Synopsys reveals challenges of 10nm finFET design flows.
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
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