Blog Topics

May 17, 2017

Matlab links up with Virtuoso for circuit analytics

Cadence Design Systems and The Mathworks have implemented the first phase of an integration program to link tools such as Virtuoso ADE to Matlab.
May 16, 2017

Cadence adapts Jasper tools for CDC and lint

Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
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May 16, 2017

Imagination sells design services, software integration to Sondrel

Engineering consultancy pays undisclosed sum for IMGworks division.
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May 15, 2017

IEDM opts for later deadline on 63rd conference

The 63rd IEDM has issued a call for papers for its conference in San Francisco in early December and has stuck with the later deadline introduced last year.
May 12, 2017

Toshiba case study describes advanced thermal simulation

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.
May 12, 2017

Advanced processes feature at VLSI in June

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
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May 11, 2017

Racyics puts FD-SOI design flow online

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.
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May 5, 2017

Embedded developers learn to become agile

Can embedded projects that call for both custom hardware and software be agile? It's a question that a conference in early May organized by UK training company Feabhas sought to answer.
May 4, 2017

Imagination to slim down to graphics core

Hit by the loss of major client Apple, Imagination Technologies plans to sell off its MIPS and Ensigma divisions. The move signals a shift away from previous plans to diversify out from graphics processors.
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May 3, 2017

Master the verification challenge of PCIe-based NVMe storage

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.
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