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Read some edited highlights from the most successful companies in Mentor's 2017 Technology Leadership Awards.

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.

IoT kettle maker changed its approach to bolster security, the company's CTO explained at the IoTSF conference in London.

Altium has rewritten its PCB-design software to improve graphics performance and provide the opportunity to port to non-Windows operating systems such as OS X.

IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.

Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.