Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Blog Topics
Accellera updates UVM reference implementation
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
Symphony raises crescendo for AMS simulation
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Netronome launches chiplet initiative for network-accelerator SIPs
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
Cadence adds deep-learning support to audio DSP
Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
IEDM to examine scaling from multiple directions
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
DVCon Europe takes in machine learning and stimulus for verification
Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
UltraSoC combines tools for cross-SoC debug and analysis
Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes
Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
White paper outlines challenges of developing machine-learning hardware
A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.
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