Ceva has developed its first processor architecture aimed squarely at deep learning.
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.
The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.
X-Fab has added a process module to its wide voltage- and temperature-range 180nm mixed-signal process that supports a set of transistors with lower 1/f flicker noise.
Minima Processor is working on the first processor cores that will be customized to use its timing-control technology to push supply voltages into the near-threshold zone.
Arm is putting together a security framework that the company is assembling to support, at least initially, IoT devices based on the Cortex v8M architecture.
Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.
Synopsys' line-up at next week's ARM TechCon includes joint presentations with Huawei and Nvidia.
ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.
View All Sponsors