Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
For the ninth year, I Love DAC badges will provide free access to the Design Automation Conference exhibition and pavilion sessions.
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
ARM has pulled together a number of forthcoming changes to its Cortex processor and Big-Little cluster architectures under the umbrella title DynamIQ, claiming they will support the increasing use of AI algorithms in servers and embedded control.
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
Intrinsic-ID has developed software that allows its PUF technology to be used in most systems that contain static memory together with a framework for managing secure keys in the supply chain.
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