IP

March 13, 2017

Open-Silicon claims RISC-V ultra-low-power first

Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
March 7, 2017

Reducing the documentation burden in ISO 26262

The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
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February 23, 2017

Ceva DSP multiplies execution units for MIMO 5G

Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
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February 14, 2017

Software brings secure IDs to almost any device

Intrinsic-ID has developed software that allows its PUF technology to be used in most systems that contain static memory together with a framework for managing secure keys in the supply chain.
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January 18, 2017

Wafer expansion hits the buffers

What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
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January 9, 2017

VLSI Symposia issue calls for papers

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
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December 22, 2016

Webinar discusses SoC security, area, and power trade-offs

SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
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December 19, 2016

White paper discusses optimising the efficiency of DDR memory subsystems

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
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December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
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November 24, 2016

Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
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