IP

April 11, 2018

Tensilica DSP extends pipeline for performance

Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
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April 5, 2018

Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolles.
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March 19, 2018

Xilinx plans reconfigurable compute for 7nm FPGA generation

Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.
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March 19, 2018

Accellera begins IP security-assurance standards effort

Accellera Systems Initiative has begun a project that may result in the creation of a standard to address security assurance for semiconductor IP cores.
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February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 28, 2018

Accellera publishes beta portable-stimulus proposal

The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.
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February 27, 2018

Synopsys UFS 3.0 IP doubles bandwidth to flash

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
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February 22, 2018

Neural networks and vector processors deployed by Ceva for 5G handsets

Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
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February 21, 2018

Arm to push integrated SIM for secure IoT

Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.
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February 21, 2018

Bulk transistor design aims for near-threshold power cuts

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
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