February 28, 2023
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
January 18, 2023
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
January 6, 2023
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
December 12, 2022
Ahead of the RISC-V Summit in San Jose, Imperas Software has issued updates to its ImperasDV verification IP for RISC-V verification and Codasip has launched a secure-processor initiative.
December 5, 2022
Imec has developed a high-endurance ferroelectric capacitor that could form the basis of storag-class embedded and standalone memories.
November 14, 2022
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
September 21, 2022
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line.
September 21, 2022
Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
August 31, 2022
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022
Imperas Software has published an open-source functional-coverage library for RISC-V cores.