The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.
Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.
Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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