IP

February 28, 2018

Accellera publishes beta portable-stimulus proposal

The Accellera Portable Stimulus Working Group has released for public review its current proposal for the verification standard it is working on.
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February 27, 2018

Synopsys UFS 3.0 IP doubles bandwidth to flash

Faster, lower power flash interface IP with built-in encryption/decryption speeds access to embedded and removable storage.
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February 22, 2018

Neural networks and vector processors deployed by Ceva for 5G handsets

Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
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February 21, 2018

Arm to push integrated SIM for secure IoT

Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.
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February 21, 2018

Bulk transistor design aims for near-threshold power cuts

Semiwise, a startup founded by University of Glasgow professor Asen Asenov and former CEO of Gold Standard Simulations (GSS), has developed a low-power CMOS transistor technology suitable for ultralow-power sensor nodes.
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February 13, 2018

Arm readying AI processor to catch up with ‘surprising’ demand

By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
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January 31, 2018

Analog blocks go digital for faster integration

Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.
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January 28, 2018

UltraSoC delivers trace for RISC-V

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
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January 23, 2018

ARM DesignStart case study demonstrates scheme’s ease-of-use

ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.
January 23, 2018

Codasip updates processor-architecture tools

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
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