Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
Panasonic and AIST have turned a resistive memory (RRAM) into a hydrogen sensor that they claim works at much lower energy than existing designs.
Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
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