IP

July 2, 2018

Tools suppliers back version 1.0 of portable-stimulus standard

Accellera has published the first release of the Portable Test and Stimulus Standard (PSS), with tools suppliers following up with software support.
June 25, 2018

Node-variant FinFET tweaks try to improve cost, performance

Foundries have taken aim at standard-cell track height and design-rule tweaks to try to improve the area efficiency and performance of derivative finFET processes.
June 21, 2018

RRAM to sniff out hydrogen from fuel cells

Panasonic and AIST have turned a resistive memory (RRAM) into a hydrogen sensor that they claim works at much lower energy than existing designs.
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June 20, 2018

Micron sees NAND powering on as DRAM struggles

Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, Micron executive claims in VLSI Symposia keynote.
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June 19, 2018

Exploring the automotive industry’s requirements for data converter IP

What does it take to build data converter IP that will meet the reliability and functional safety requirements of the automotive industry?
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June 14, 2018

Accellera signs off on SystemC control standard

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
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May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
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May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 22, 2018

IEDM 2018 aims to span quantum, neuromorphic and CMOS devices

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
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May 2, 2018

Arm adds tamper resistance to M-series core

Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
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