IP

UltraSoc has donated to the RISC-V Foundation a specification for processor trace to try to provide the ecosystem with a common way of exporting runtime data to software tools.

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.

Semiconductor supplier Microsemi has used the Eclipse open-source IDE platform to develop a Windows-based toolchain for CPUs that supports the RISC-V instruction set.

Vendor concentrates on memory IP products at 2017 Design Automation Conference.

Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace.

A year on from the last Computex and the launch of the Cortex-A73 and Mali-G71, ARM has launched a new trio of processors aimed not just at smartphones this time but servers and driver-assistance systems.

Engineering consultancy pays undisclosed sum for IMGworks division.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

Hit by the loss of major client Apple, Imagination Technologies plans to sell off its MIPS and Ensigma divisions. The move signals a shift away from previous plans to diversify out from graphics processors.

Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.