IP

By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.

Movellus has launched the first of a series of IP-creation tools with one that will build all-digital PLLs and integrate them into a design.

UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.

ARM and Mentor describe a proof-of-concept project using free tools and IP to combine AMS and digital.

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.

IP provides key building blocks for building better video and audio playback devices using HDMI 2.1

Ceva has developed its first processor architecture aimed squarely at deep learning.

Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.