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Codasip has put support for a set of instruction extensions intended to secure memory into its RISC-V core designs.

X-Fab has made it possible to put galvanic isolation based on capacitive coupling directly into chips made on its XA035 process.

SureCore and Intrinsic have teamed up to provide a way to implement resistive random-access memory as an SoC-embeddable technology.

Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.

Imperas Software has worked with AI specialist Tenstorrent to create and distribute a model of the Ascalon processor core.

This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.

The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.