IP

June 25, 2014

Sensor-hub infrastructure moves to open source

With the aim of accelerating the development of applications and algorithms that harness sensor fusion, startup Sensor Platforms has released as open source its Open Sensor Platform (OSP).
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June 25, 2014

Don’t just whine – it’s time for you to help shape DAC 2015

Any conference can only be as good as the feedback it gets. And next year's DAC team is actively looking for yours. It'll be worth your time.
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June 6, 2014

eSilicon to cut costs of ASIC development for IoT, other markets

Online portals enable ASIC designers to explore IP and delivery options, enabling lower-cost markets such as IoT
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June 2, 2014

Samsung certifies Synopsys tools, IP at 14nm

Samsung, Synopsys and ARM have been working together to create a finFET design ecosystem.
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June 2, 2014

Synopsys uses virtual prototyping kits to kick start IP integration

Synopsys is porting its IP to a series of virtual prototyping kits in a plan to cut the amount of time that it takes to integrate new high-speed interfaces such as USB 3.0
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May 29, 2014
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IP takes center stage in push towards systems engineering

At DAC 2014, some 30 per cent of exhibitors are IP suppliers, offering design services or both, demonstrating how system-level design is about building on what has gone before.
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May 20, 2014

Vorsprung durch 3D technik for Audi

The automotive sector could become one of the key markets for 3D integration according to the head of Audi's progressive semiconductor program.
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May 20, 2014

Cadence signs with ARM for core optimizations

Cadence Design Systems has signed up for a licence to ARM cores that will let the EDA supplier optimize support for 32bit and 64bit Cortex processors in its tools.
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May 17, 2014

Cadence ports IP and qualifies tools for 28nm FD-SOI

Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
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April 24, 2014

Altera finds a way to cheaper floating point in FPGAs

Altera has revealed that the DSP blocks in the Arria 10 FPGAs contain the logic needed to make them work as IEEE754-compliant floating-point units.
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