IP

Achronix is introducing an FPGA architecture that pulls a full network-on-chip into the programmable-logic fabric combined with hardened matrix-math processors for AI.

Mentor is active across the program and its main and Verification Academy booths within the exhibition in Las Vegas.

EDA and IP supporters of the new event see the goal of greater integration with the electronic systems supply chain as fundamental to their involvement.

Accellera is trying to standardize extensions to UVM for mixed-signal design.

Large-scale MCMs and novel device architectures bookend the papers on machine learning at VLSI Symposia in an event that will also cover chiplet integration and other topics.

Synopsys and GLOBALFOUNDRIES are developing a portfolio of automotive IP for the chipmaker’s 22nm fully depleted silicon-on-insulator (22FDX) process.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.

DVCon Europe has added embedded software, digital twin, machine learning, and RISC-V to the topics the conference organizers want to cover.

Not only has Microsoft decided to make a compression algorithm intended for data centers open source, the company the company is providing its own RTL to anyone who wants to implement it in silicon.

The ODSA Workgroup formed by Netronome and others is looking to adopt the PIPE standard for interconnecting chiplets as it starts work on a proof-of-concept module.