Ceva has launched a software package intended to streamline the porting of convolutional neural network implementations to the XM4 DSP core.
Memory efficiency has driven the design of the latest video and image processor core developed by Cadence Tensilica.
A novel approach to 3D NAND will be among the presentations at the International Electron Device Meeting to be held in Washington, DC in December.
DVCon Europe has published the technical program for its upcoming November conference in Munich, Germany.
Low-power IP and software portfolio includes security hardware, Bluetooth and ISB interfaces, configurable processors and sensor subsystems
Synopsys updates its FPGA-based prototyping system to offer more capacity, higher speed, faster bring-up, better ROI
Menta has launched a family of off-the-shelf IP cores aimed at TSMC’s 28nm processes to provide reconfigurability for SoCs.
Synopsys delivers reconfigured PHY IP to support reversible USB Type-C connector.
Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
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