IP

November 24, 2016

Codasip adopts UltrasSoC debug for RISC-V cores

Codasip, a provider of processor cores based on the open-source RISC-V processor IP, has teamed up with UltraSoC to incorporate hardware debug and security features.
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October 25, 2016

ARM brings security to Cortex-M family

ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.
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October 24, 2016

Serdes deal to push copper server interconnect to 100Gbit/s

A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
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October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
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October 11, 2016

Achronix moves into embedded FPGA

Achronix has decided to offer the FPGA technology it has developed as a set of embeddable cores.
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October 10, 2016

Ceva aims to displace ARM in IoT nodes with combo processor

Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
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October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
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September 27, 2016

Ceva adds hardware to speed up deep learning

Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
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September 20, 2016

UltraSoC to support RISC-V

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
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September 20, 2016

Debut for safety-critical ARMv8 core

ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.

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