Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (March 20)
Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
ARM has launched a 64bit processor core aimed at high-end mobile phones, coupled to a new graphics processor and cache-coherent interconnect.
ARM has picked up TÜV Süd certification for a version of its C compiler and produced an ISO 26262 documentation pack for the Cortex-R5 processor
Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
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