Ten cores in three clusters help match smartphone power/performance to app load and usage at MediaTek, thanks to Synopsys design exploration tools
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Electronics design needs to cope with a combination of major brands and tiny start-ups looking to exploit its skills even where their resources are thin.
Synopsys develops portfolio of ASIL B ready IP, and invests in AEC-Q100 testing and TS 16949 quality management, to ease automotive SoC qualification.
S3 Group has launched the second in a family of low-power successive-approximation ADCs, with a design that supports sample rates up to 320MS/s.
CAST and SoC Solutions have teamed up to put together pre-integrated platforms, with designs that reach down into the 8bit space.
Embedded SRAM IP said to reduce dynamic, static power on FDSOI at cost of extra 10% area
An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.
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