UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
ARM is extending its work on ISO 26262 safety packages for automotive systems beyond the Cortex-R devices supported in a documentation release earlier this year.
Cadence has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables.
Deep learning offers the next major opportunity for specialist processors, Qualcomm's Karim Arabi claimed in his keynote at Mentor Graphics’ U2U in San Jose.
Designers will need to take crime into account as part of their design signoff process, Wally Rhines argued in his keynote at Mentor Graphics' U2U San Jose 2015 conference.
The Athena Group says it has developed countermeasures against side-channel attacks for its IP that offer the best protection currently available.
ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.
Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (March 20)
Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
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