The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
ARM has pulled together a number of forthcoming changes to its Cortex processor and Big-Little cluster architectures under the umbrella title DynamIQ, claiming they will support the increasing use of AI algorithms in servers and embedded control.
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
Ceva's latest iteration of its XC architecture aims at the intensive DSP required for 5G basestations.
Intrinsic-ID has developed software that allows its PUF technology to be used in most systems that contain static memory together with a framework for managing secure keys in the supply chain.
What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
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