IP

November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
October 31, 2018

Cadence adds deep-learning support to audio DSP

Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
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October 22, 2018

IEDM to examine scaling from multiple directions

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
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October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
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October 9, 2018

Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services (AWS) or Microsoft Azure.
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September 26, 2018

SureCore SRAM tuning service aims for lower power

SureCore is introducing an IP customization service intended to deliver SRAM cores tuned to specific power and performance requirements for wearable, wireless, augmented reality, and IoT devices.
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September 26, 2018

DVCon Europe keynotes take in digital twin and IoT concepts

Two keynote speakers have been announced for DVCon Europe 2018, which takes place next month.
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September 19, 2018

Cadence culls zeroes for faster neural throughput

Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
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August 28, 2018

GlobalFoundries stops 7nm work to focus on existing processes

GlobalFoundries has decided to put development of its 7nm process on the backburner and focus on its existing finFET and FD-SOI processes.
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August 3, 2018

MPW service arrives for RRAM

Research institute Leti and low-volume wafer service CMP are cooperating on a project to let fabless chipmakers explore the use of non-volatile resistive RAMs in their designs.
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