IP

February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
Article  |  Tags: ,   |  Organizations:
February 16, 2015

CDNLive Silicon Valley: last chance for early bird discount

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (March 20)
Article  |  Tags: ,   |  Organizations: ,
February 11, 2015

Accellera sets up group for one-stop verification stimulus

Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
Article  |  Tags: , ,   |  Organizations:
February 3, 2015

ARM to upgrade smartphone processing with Cortex-A72 combination

ARM has launched a 64bit processor core aimed at high-end mobile phones, coupled to a new graphics processor and cache-coherent interconnect.
Article  |  Tags: , , ,   |  Organizations:
January 27, 2015

ARM to provide safety docs for real-time processors

ARM has picked up TÜV Süd certification for a version of its C compiler and produced an ISO 26262 documentation pack for the Cortex-R5 processor
Article  |  Tags: , , , , ,   |  Organizations:
January 14, 2015

Cadence updates Xtensa with memory and power saving features

Cadence Design Systems has launched the 11th generation of Tensilica Xtensa customizable processors, with changes for VLIW, power-saving caches and memory accesses.
Article  |  Tags: , , ,   |  Organizations:
December 11, 2014

Use-cases drive high-level verification tool

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
October 28, 2014

10Gbit/s USB 3.1 IP and verification support on the way

USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
Article  |  Tags: , , , ,
October 14, 2014

ARC core focuses on embedded Linux applications

Synopsys updates ARC core to improve support for embedded Linux and other advanced operating systems such as Android
Article  |  Tags: , , , ,   |  Organizations:
October 7, 2014

Minimal 32bit IP cores tackle connected devices market

Minimal IP cores are meant to serve broader market than IoT, using revised instruction set to increase code density, save on chip memory and enable security
Article  |  Tags: , , , ,

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors