IP

May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
Article  |  Tags: , , ,   |  Organizations: ,
May 25, 2016

ECC crypto code and core aim for home automation

Oberon Microsystems has ported a set of low-overhead cryptographic codes suitable for Apple's HomeKit to the Cortus APS3RP 32bit processor core.
Article  |  Tags: , , , ,   |  Organizations:
May 18, 2016

ARM completes multicore test chip on 10nm finFET

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
Article  |  Tags: , , ,   |  Organizations: ,
May 3, 2016

Cadence boosts MAC count for neural networks

Cadence Design Systems has increased the throughput of its vision-oriented DSP family to cater for deep-learning applications.
March 31, 2016

Meet the Electronic System Design Alliance

The EDA Consortium is rebranding and extending its activities to better reflect all the tools and services that now comprise IC design.
Article  |  Tags: ,   |  Organizations: ,
March 31, 2016

53rd DAC conference program announced

The 53rd Design Automation Conference has published its program for the upcoming event in Austin, Texas, which will include keynotes from AMD, nVidia, and NXP Semiconductors and tracks that connect electronics to biology.
Article  |  Tags: , , , , ,   |  Organizations: , ,
March 16, 2016

MEMS contest launches at DATE

The DATE 2016 conference saw the launch of a competition to encourage novel designs using MEMS technology.
Article  |  Tags: , ,   |  Organizations: , ,
March 11, 2016

GSA on how to reinvigorate silicon business models

Open-source hardware, in-field configurability, and a hardware-plus-services approach could protect margins as the IoT hammers down costs, says GSA report.
March 9, 2016

IP implementation variety drives latest partnerships

Mentor Graphics' recent deal with ARM illustrates how proliferation in design is influencing deals between tool and IP vendors.
March 1, 2016

Mentor builds out verification IP for memory

About 1,600 new UVM System Verilog verification IP memory models will cut testbench development time and offer more time to increase coverage.

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors