Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
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