UltraSoC has added deadlock detection capabilities to its multicore onchip debug framework.
Foundry strikes two more Internet of Things subsystem deals for its 55nm ULP process based on Cadence Tensilica and Imagination MIPS/PowerVR cores.
By widening the range of resources that can be tracked within an SoC, Ultrasoc says it has uncovered ways to make debug a long-term tool for complex multicore designs.
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to show how chipset designs would fare under a variety of software-based power-management algorithms.
Online conference discusses software testing for avionics and security, code coverage, agile methodologies, behaviour-driven development and more
An overview of Cadence's activities at DAC and a last-minute call-out if you want to register for its breakfast and luncheon sessions.
Review highlights from Mentor's activities at DAC and grab your last chance to register for in-depth technical sessions.
Blocks' promo video says its work was 'Funded by Intel' but Qualcomm has announced that the modular watch company will be using its Snapdragon 400.
Everybody knows the words. Everybody has a different definition. Did calling the next big thing 'The Internet of Things' actually create a hindrance not a help?
It wasn't just ARM and TSMC that launched a 55nm IoT platform this week. Across the Taiwan Strait, Brite and SMIC have unveiled a similar offering. The competition could tell us a lot about the IoT market's future.
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