Embedded

December 15, 2016

Benchmark effort to look at IoT security performance

EEMBC has launched a benchmarking effort to test the performance of security and crypto-functions on embedded devices.
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December 6, 2016

Security group publishes first guidelines

The UK's IoT Security Foundation has published the first set of documents intended to provide best-practice guidelines for developers of embedded systems.
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November 14, 2016

Multicore Association to update performance-estimation standard

The Multicore Association has started work on the second version of its SHIM performance-modeling standard for SoCs.
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November 9, 2016

Multicore standard works on fast communications

Work by the Multicore Association to provide a standard way for applications running on different processors to communicate with each other is leading to active implementations.
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October 25, 2016

ARM brings security to Cortex-M family

ARM has launched the first of a series of Cortex-M series microcontrollers based on the V8M architecture that incorporate the Trustzone security mechanism.
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October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
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October 13, 2016

ESD Alliance to describe system shift at DVCon Europe

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
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October 10, 2016

Ceva aims to displace ARM in IoT nodes with combo processor

Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
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September 27, 2016

Ceva adds hardware to speed up deep learning

Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
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September 20, 2016

UltraSoC to support RISC-V

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
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