October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
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October 13, 2016

ESD Alliance to describe system shift at DVCon Europe

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
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October 10, 2016

Ceva aims to displace ARM in IoT nodes with combo processor

Ceva has decided to take its VLIW architecture into the world of IoT sensor nodes and smart wearables with the launch of the X1 processor core.
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September 27, 2016

Ceva adds hardware to speed up deep learning

Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
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September 20, 2016

UltraSoC to support RISC-V

UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
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September 20, 2016

Debut for safety-critical ARMv8 core

ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
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August 15, 2016

EEMBC updates automotive benchmark for scalability tests

EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
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August 12, 2016

Chinese dates set for Asia-Pacific editions of Mentor Forum

Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
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July 26, 2016

Cadence adds floating point to Fusion

Cadence Design Systems has added floating-point to its latest core intended for embedded signal processing.
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