Xilinx plans to make reconfigurable computing the focus of its upcoming generation of FPGAs, which will be made on a 7nm finFET process at TSMC and expected to start sampling next year.
June's DAC will see the culmination of a contest involving more than 100 teams vying to demonstrate the best use of machine learning on embedded hardware in a flying drone.
With the aim of making it easier for embedded devices to cooperate in an IoT environment, Mentor has launched a cloud connectivity and management framework.
Ceva has decided to include neural network, vector processing and customized instruction sets in an IP platform for 5G NR terminals.
Arm plans to use its cryptography cores and technology from its Simulity Labs acquisition to SIM-based security into IoT devices.
Slovenian startup Red Pitaya has added a front-end module and firmware to its FPGA-based StemLab board to create a customizable vector network analyzer (VNA) and RF tester.
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
UltraSoC has released its first implementation of processor trace for cores based on the RISC-V instruction set.
Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Ceva has developed its first processor architecture aimed squarely at deep learning.
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