EDA

Silicon Cloud is preparing to expand access to its network-based design environment beyond the universities using it today to commercial users

Electronics design needs to cope with a combination of major brands and tiny start-ups looking to exploit its skills even where their resources are thin.

Following the acquisition of Jasper Design Automation last year, Cadence Design Systems is widening the target base of applications for formal verification, covering tasks from bug hunting through accelerated simulation to 'superlinting'.

Silicon Impulse program adds partners to ease industrialisation of ultra-low power IC designs based on FD-SOI processes

Altera is using a combination of Intel's 14nm process technology and multidie packaging to boost the logic-cell count for its FPGAs, together with a superpipelining strategy to help balance area and clock speed.

Gold Standard Simulations (GSS) has launched a tool intended to help fabless chipmakers squeeze more out of existing processes rather than accept the risk and expense of moving to more advanced, finFET-based processes.

Atrenta's SpyGlass line and others to be absorbed in Verification Continuum and Galaxy as part of EDA's latest major consolidation.

IBM to offer end-to-end IC design flow on its own infrastructure in PAYG EDA model.

Invionics will be using its software environment to create a custom tool within just two days at the 52nd DAC.

OneSpin Solutions has used its formal-verification technology as the basis for an app intended for ISO 26262 projects that analyzes the ability of a design to deal with fault conditions.