EDA

April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023

Achieving functional coverage of multi-language designs

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
April 17, 2023

DVCon Europe adds research track

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
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April 4, 2023

Curvilinear layout looks to wider adoption with mask speedups

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
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March 30, 2023

SEMI predicts strong 300mm growth to 2026

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
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February 28, 2023

Imperas and Synopsys team on RISC-V debug

Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
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January 18, 2023

Accellera forms CDC working group and takes security standard to IEEE

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
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January 6, 2023

DVCon Europe best paper speeds up memory-controller tests

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
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January 4, 2023

A*Star lays out SiP applications choices at IEDM

The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
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December 9, 2022

Imec adds MOL layer to potentially cut cell size 20%

Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
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