October 24, 2016
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
October 24, 2016
At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
October 17, 2016
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
October 13, 2016
Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
October 10, 2016
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
September 13, 2016
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
August 27, 2016
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
August 24, 2016
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
August 15, 2016
Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
August 12, 2016
Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.