Streamlining analog fault simulation
Analog fault simulation times have barely fallen for two decades but that is beginning to change.
EDA
Mentor launches new Strato emulation platform
StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.
DVCon US 2017 preview: Mentor Graphics
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
SPIE Advanced Lithography preview: Mentor Graphics
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
Overcome IoT edge challenges with integrated flows
IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.
Wafer expansion hits the buffers
What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
VLSI Symposia issue calls for papers
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
IMEC stacks nanowire transistors together on CMOS
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Siemens agrees deal to buy Mentor Graphics
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
Webinar focuses on Eldo RF verification of Tanner-based designs
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
PLATINUM SPONSORS
View All Sponsors