EDA

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking

Oski Technology will offer a range of daily presentations at its DAC 2017 and useful technical advice in the main conference program.

EDA's leading association will be visible across the program at DAC 2017 from CEO interviews to social events.

Verific has acquired the Invio custom-tool development environment developed by Invionics Software.