EDA

The massive complexity of 5G and automotive systems and the need for advanced verification techniques set the scene for DVCon Europe this year.

GlobalFoundries intends to offer a 12nm FinFET process as a stepping stone from its 14nm process.

ARM, Xilinx, Cadence Design Systems, and TSMC have agreed to produce a test chip for the CCIX project.

DVCon Europe 2017 has announced two keynote speakers for the conference to be held in Munich, Germany in mid-October.

Automotive test has never been easy. Safety made sure of that. But the move to autonomous vehicles is making it more challenging still.

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.

ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.