EDA

August 22, 2023

Accellera group formed to work on federated simulation

Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
August 8, 2023

Catch up with the state-of-the-art in ‘shift left’

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.
July 25, 2023

Verification Futures heads to the US in September

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.
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July 24, 2023

Backside power shows promise but more complex manufacturing

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.
July 11, 2023

AI’s possible roles in verification covered at VF2023

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.
July 10, 2023

Calibre ‘shifts left’ into place and route

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R
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July 10, 2023

Siemens fuels custom IC flows with artificial intelligence

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.
July 4, 2023

Co-design underpins infrastructure acceleration at Google

At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
June 1, 2023

Does 2.5DIC call for IC design tools for the packaging?

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
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May 30, 2023

Charting the path for machine learning in functional verification

A comprehensive review of ML's potential and its current use identifies challenges ahead.

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