EDA

October 25, 2023

Image sensors shrink at IEDM

This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
October 25, 2023

VLSI Symposium 2024 looks to bridge digital and physical

The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
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October 24, 2023

Flow evolution for the 3DIC/chiplet age

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
October 16, 2023

Accellera updates portable stimulus standard

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
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October 9, 2023

ITC 2023 preview: Siemens DIS

From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
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October 9, 2023

Tessent speeds ‘shift left’ drive for test at RTL

Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.
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October 6, 2023

Fast instruction simulator expands to Arm

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
October 5, 2023

Vertical integration expands at IEDM

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
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October 3, 2023

Siemens and CEA link up on AI-assisted digital twins

Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.
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September 6, 2023

HPC and AI provide keynote focus at DVCon Europe

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.

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