EDA

February 25, 2015

Cadence combines HLS tools in Stratus release

Cadence Design Systems has tied together the Forte Synthesiser and the internally developed C-to-Silicon tools into a new high-level synthesis (HLS) environment the company has titled Stratus.
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February 16, 2015

CDNLive Silicon Valley: last chance for early bird discount

The $99 discount registration price for Cadence's main US user conference will no longer be available after Friday (March 20)
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February 11, 2015

Accellera sets up group for one-stop verification stimulus

Accellera has set up a working group to develop a language-independent way of capturing and managing test stimuli that can be used across a wide range of verification environments.
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February 3, 2015

Speeding up simulation using native System Verilog transactors

Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
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January 19, 2015

Ambiq uses subthreshold techniques to cut power on ARM MCUs

Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power consumption at levels normally associated with an M0+.
January 7, 2015

CEA-Leti deals with heat issue on monolithic 3DIC

At IEDM 2014, CEA-Leti presented a technique that prevents damage to base-layer transistors in monolithic 3DIC processes. As work progresses, the institute is preparing to receive 3DIC designs in 2017.
January 5, 2015

Cadence high-level synthesis changes deal with congestion

SystemC coding style can lead to excessive congestion in the logic generated by high-level synthesis. Cadence described how it is attacking the issue at its recent Front-End Design Summit.
December 18, 2014

Gary Smith EDA: PCB ‘a door to the future’ but ‘slow take-off’ for ESL

The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
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December 16, 2014

14nm/16nm finFETs debut at IEDM

The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes - this time with finFETs.
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December 11, 2014

Use-cases drive high-level verification tool

Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.

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