EDA

June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
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June 20, 2017

Siemens sees Mentor helping to build fast digital twins

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
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June 20, 2017

ARM puts Cortex-M3 into DesignStart program

ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.
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June 19, 2017

Joe Costello claims IoT will drive wave of design

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.
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June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
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June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
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June 16, 2017

DAC 2017 preview: Baum

Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
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June 15, 2017

Early access view of portable-stimulus standard released

Accellera has released an Early Adopter version of the upcoming Portable Stimulus Specification.
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June 15, 2017

DAC 2017 preview: Breker

At a DAC that will feature the arrival of the Accellera portable stimulus standard, Breker will demonstrate its implementation of the Early Adopter release of the specification.
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June 15, 2017

Smart code editor adds SystemVerilog support

Sigasi has added support for SystemVerilog to its Sigasi Studio tool, which uses a built-in parser to perform more reliable syntax highlighting and error checking
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