October 26, 2016

Cadence maps out safety plan for semiconductor-design tools

Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
Article  |  Tags: , ,   |  Organizations:
October 24, 2016

Serdes deal to push copper server interconnect to 100Gbit/s

A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
Article  |  Tags: , ,   |  Organizations:
October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Article  |  Tags: , , , , ,   |  Organizations:
October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Article  |  Tags: , ,   |  Organizations:
October 13, 2016

ESD Alliance to describe system shift at DVCon Europe

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Article  |  Tags: , , , ,   |  Organizations:
October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Article  |  Tags: , , , , ,   |  Organizations:
September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Tags: , , , ,   |  Organizations:
August 27, 2016

Creating a reference design flow for 10nm processes: video

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Article  |  Tags: , ,   |  Organizations: ,
August 24, 2016

Cadence building photonics environment around Virtuoso

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
Article  |  Tags: , ,   |  Organizations:
August 15, 2016

SystemC materials move to Apache 2.0 license

Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Article  |  Tags: ,   |  Organizations:


Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors