EDA

June 19, 2018

DAC 2018 preview: ESD Alliance

The Electronic System Design Alliance will discuss its recent decision to join SEMI and highlight DAC's new Infrastructure Alley.
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June 19, 2018

DAC 2018 preview: Baum

Power analysis specialist will showcase the 2.0 edition of its PowerBaum analysis and modeling suite at DAC.
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June 18, 2018

Switch to orbit mode boosts MRAM on 300mm wafers

Imec will at this week’s VLSI Symposia describe how it fabricated a form of magnetic memory suitable for use as a non-volatile cache onto 300mm wafers using CMOS-compatible processes.
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June 14, 2018

Accellera signs off on SystemC control standard

Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
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June 6, 2018

Synopsys speeds PrimeTime with AI

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design
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May 24, 2018

Case study demonstrates 59% extra power savings for HPC

Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
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May 23, 2018

Pillar transistor points to smaller SRAMs at 5nm

Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
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May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 22, 2018

IEDM 2018 aims to span quantum, neuromorphic and CMOS devices

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
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May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
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