Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Cadence Design Systems has designed its Palladium Z1 emulator to fit into the corporate data-center, improving virtualization and availability aspects of the system’s design.
But the bridge standard's European backers still need greater support from the big EDA vendors.
High powered alliance develops TLM standards to address growing automotive and IoT concerns.
ARM has moved back into system-level modelling with the decision to buy the tools and models developed by Carbon Design Systems
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