EDA

April 25, 2018

Anne Cirkel recognized for advancing role of women in electronics design

Mentor executive, former Design Automation Conference chair and Tech Design Forum journal founder to receive Marie R. Pistilli Award at DAC 2018.
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April 20, 2018

SEMI-ESDA tie-up aims to extend EDA’s global reach

Cooperation in key verticals such as automotive and changes for DAC as well as global conference outreach underpin EDA association's move.
April 10, 2018

Cadence tunes Virtuoso for 5nm and SIP

Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
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April 9, 2018

DAC keynotes and sessions aim for AI

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.
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April 5, 2018

Leti releases photonics design kit for Synopsys PhoeniX OptoDesigner suite

PDK enables photonics prototyping on MPW runs and compatibility with volume production at STMicroelectronics at Crolle.
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April 5, 2018

Mentor aims to grow emulation with lower gate-count hardware

Strato emulator family adds modular boxes that can build from 640K and 1.25B gate-counts for automotive, mil/aero markets and 'digital twin' strategies.
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March 23, 2018

Layout schema generation speeds early-stage yield learning

LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
March 21, 2018

VLSI Symposia adds day for AI

June's Symposia on VLSI Technology & Circuits will bring together a number of industry trends that extend from implantable biomedical applications to machine learning and cloud computing under the banner of technologies for ‘smart living’.
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March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

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