EDA

May 26, 2016

Real Intent extends Meridian Constraints for untimed paths

Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
May 25, 2016

Register tools appear ahead of DAC

Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
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May 24, 2016

DAC 2016 preview: Gary Smith EDA

The company's annual 'What to see' list is now available for download and highlights some of EDA's less recognized areas of innovation.
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May 23, 2016

Cloud analysis comes to power grid design

Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
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May 18, 2016

ARM completes multicore test chip on 10nm finFET

ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
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May 5, 2016

Functional safety and high reliability for FPGA designs – eight videos show you how

Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
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April 20, 2016

Toward easier, faster test pattern simulation

Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.
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April 13, 2016

User2User preview: Silicon Valley edition rolls out this month

Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
April 7, 2016

SNUG 2016: Intel, TSMC, GloFo back post-finFET research at UC Berkeley

But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
April 5, 2016

Cadence moves into safer design with Virtuoso changes

Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.

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