Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
The first in a series of articles on how various vendors are addressing the flow's most challenging task looks at Mentor's strategy for emulation.
But some research and process collaboration is set to continue in the background as Samsung, GlobalFoundries and IBM chart their own priorities.
Enterprise Verification Platform adds cross-over SystemVerilog, UVM, and UPF support for Veloce alongside new hardware and software debuggers.
The 2013 edition of the International Technology Roadmap for Semiconductors has been published. The latest set of tables underlines the slowdown in some aspects of scaling, particularly when it comes to metal interconnect.
The 51st Design Automation Conference, to be held in San Francisco in early June, is offering free exhibit floor entry for the full three days.
Registration is free-of-charge to attend Mentor, Oracle and Samsung keynotes and choose from nine technical tracks at one-day event.
Deal quashes rumors that Altera was about to move its cutting edge production back to TSMC, but nor does it appear to be 'exclusive' for 3D products.
IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
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