Testbench connections often depend on the virtual interface feature of SystemVerilog but other options - like abstract classes - can help.
In the first of a weekly series on China's evolving design sector, we look at how the Mentor President and CEO identifies some of the key drivers.
IEDM plans to expand its range of coverage for the 2019 event to encompass a range of novel computing platforms, from neuromorphic architectures to machines that emulate thermodynamic systems.
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
A new paper describes a case study for a pressure-sensing IoT application based on the ARM DesignStart platform and Mentor IoT tool flow.
Early access to tools for new processes is helping Moortec deliver IP to determine the real-time health of on-chip circuits.
A report put together by Europe's HiPEAC high-performance computing research network argues computing is at an architectural turning point
Physical verification challenge of large SoCs on leading-edge processes detailed in video series
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
View All Sponsors