EDA

August 11, 2017

Keynotes announced for DVCon Europe

DVCon Europe 2017 has announced two keynote speakers for the conference to be held in Munich, Germany in mid-October.
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July 7, 2017

How automotive test is evolving for the age of autonomous vehicles

Automotive test has never been easy. Safety made sure of that. But the move to autonomous vehicles is making it more challenging still.
June 27, 2017

Sonics adds heat-aware DVFS to SoC power controller

Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling, along with the ability to tune settings according to temperature.
June 27, 2017

Cliosoft aims to bring cooperation to design management

Cliosoft sees a merging of social features and design-data repositories as driving more efficient reuse in chipmakers, bringing them together in its recently launched DesignHub product line.
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June 21, 2017

Panels see congestion and resistance dominate the leading-edge node battle

Placement-aware synthesis and an array of post-layout recovery steps have helped drive up the clock speed and silicon utilization of a series high-end SoCs on leading-edge processes developed by customers of Synopsys' implementation tools.
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June 20, 2017

Siemens sees Mentor helping to build fast digital twins

An emulator that extends the reach of hardware acceleration into the world of multiphysics analysis could result from the merger of Siemens PLM Software with Mentor.
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June 20, 2017

ARM puts Cortex-M3 into DesignStart program

ARM has expanded its DesignStart program by providing access to the Cortex-M3 as well as the M0 with no up-front licence fee.
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June 19, 2017

Joe Costello claims IoT will drive wave of design

Former Cadence CEO tells DAC the IoT will lead to a burgeoning of chip design starts, followed by a brutal consolidation.
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June 18, 2017

TSMC encapsulates CoWoS for supersized SiP

TSMC encapsulated the multiple chips assembled on a 1200mm2 silicon substrate to cut the chance of damage from warping with the company's CoWoS2 SiP technology.
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June 18, 2017

Samsung 7nm uses EUV and split fin widths to push speeds

EUV and fin optimization help build Samsung's upcoming 7nm process, the company discloses at the VLSI Technology Symposium.
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