EDA

August 19, 2014

Simulations point to better performance for Intel 14nm finFET

Gold Standard Simulations has run simulations to work out how much of an improvement Intel's new rectangular shape represents.
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August 18, 2014

Power and clocking at 20nm force changes in FPGAs

Design for the 20nm generation of processes has revealed power and clocking issues for the two major FPGA manufacturers presentations at Hot Chips revealed.
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August 13, 2014

Thermal limits challenge Hot Chips power pair

Two of the custom designs presented at the 26th Hot Chips in Cupertino exemplified the problems caused by increasing power density and the benefits of looking at heat removal at the system level.
August 8, 2014

Custom instrumentation helps build models for more advanced RF amplifiers

High peak-to-average ratios inherent in 4G/5G modulation schemes are driving the circuitry controlling RF PAs to become more modeling-oriented.
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August 7, 2014

NI aims to bring design and production closer with chip-test plan

National Instruments plans to build an ecosystem around semiconductor test that could provide a missing link between the design process and production.
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August 5, 2014

Cadence takes Voltus to transistor level

Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.
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July 25, 2014

GlobalFoundries licenses atomistic TCAD simulator toolchain

Foundry licenses atomistic TCAD simulator to better understand key aspects of advanced process nodes.
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July 17, 2014

Cadence brings FPGA prototyping and emulation into sync

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
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July 15, 2014

Cadence targets finFETs with RC extraction speedup

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
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