EDA

June 30, 2015

Chipmakers see 3x test-pattern saving in embedded-test logic

Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
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June 29, 2015

FastSpice update improves parallelism and adds wreal support

The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
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June 25, 2015

X-Fab updates 180nm SOI process for automotive and industrial applications

Foundry claims isolation and device integration advantages for 180nm SOI process, help to absorb extra costs of SOI wafers
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June 23, 2015

Sonics updates tune memory and link width for speed and power

The latest release of the SonicsGN NoC infrastructure provides speedups for multichannel memories.
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June 19, 2015

Tanner integration to assist Mentor in IoT and photonics

Following Mentor's acquisition of Tanner EDA, management expect the integration will help with a drive into IoT applications and systems that need to go beyond standard IC lithography.
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June 18, 2015

The road to 7nm sees patterning multiply

Is the industry ready to go beyond 10nm when it comes to lithography? Lithography researcher Professor David Pan sees design and process co-operation as the key approach.
June 16, 2015

Collaboration let HiSilicon accelerate 16nm finFET plans

HiSilicon claims close collaboration with foundry and EDA tools partners helped speed up plans to tape out the first 16nm finFET-based design through TSMC.
June 11, 2015

Data mining tools trawl for IC icebergs

Dassault Systèmes and IC Manage have each developed "big data" mining software tools to track the progress of chip-design projects
June 11, 2015

Two-day app challenge results in RTL power analyzer

For DAC 2015, Invionics set itself the challenge of developing a custom tool in 48 hours based on votes for ideas provided by visitors to the show.
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June 10, 2015

SoC verification ‘should use software more’

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language

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