FinFETs for 7nm and below processes will be able to integrate high-mobility III-V materials despite being built on silicon processes, thanks to recent work by imec.
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.
Cadence Design Systems uses parallelism in its Voltus tool to provide faster IR drop analysis and bridge static timing and IC-level power-integrity analysis.
Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Jasper Design Automation has developed a tool that analyzes RTL and gate-level HDL for hidden paths that may expose on-chip secure elements to hackers.
Real Intent CTO Pranav Ashar talks about GALS: the reasons for and against using asynchronous protocols for chip-crossing communications and what to do about verification.
HP is throwing open its doors to other companies to bring in the necessary hardware and low-level software to build a new generation of servers, each specialized to a workload.
ARM has launched at TechCon its own crop of online forums intended to let engineers collaborate and share ideas and has asked for IoT ideas.
Memoir Systems has developed a set of memory controller IP cores that exploit common access patterns used by processors in network switches to improve performance and power consumption
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