German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
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