DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.
A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.
Startup launches an analog-circuit migration and optimization tool that uses less simulation time than traditional approaches the company claims.
Menta SAS has launched an embedded FPGA core family that improves density over previous versions.
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