EDA

November 15, 2016

Siemens agrees deal to buy Mentor Graphics

German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
November 11, 2016

Webinar focuses on Eldo RF verification of Tanner-based designs

On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
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October 26, 2016

Cadence maps out safety plan for semiconductor-design tools

Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
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October 24, 2016

Serdes deal to push copper server interconnect to 100Gbit/s

A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
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October 24, 2016

7nm finFET process techniques lead IEDM lineup

At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
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October 17, 2016

Portable stimulus gears up to accelerate verification

Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
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October 13, 2016

ESD Alliance to describe system shift at DVCon Europe

Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
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October 10, 2016

Cadence packages VIP for ten protocols

Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
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September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
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August 27, 2016

Creating a reference design flow for 10nm processes: video

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
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