The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
ARM and Tanner EDA aim to chart a path toward cheaper, easier to realize designs for the embedded and Internet-of-Things markets.
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
The Verification Futures conference organized by European EDA consultancy TV&S returns for its seventh year in early April with a focus on safety and security in the growing area of cyber-physical systems.
The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.
Three Mentor divisions - Embedded, PADS and Tanner EDA - will present their latest innovations during the conference and exhibition in Nuremberg next week.
Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Analog fault simulation times have barely fallen for two decades but that is beginning to change.
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