Analog fault simulation times have barely fallen for two decades but that is beginning to change.
StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.
The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.
The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.
IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.
What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
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