The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).
Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.
Solido aims to bring the types of machine-learning techniques the company has used for its physical-analysis tools to a wider range of EDA tools through the launch of its ML Labs initiative.
Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.
For the ninth year, I Love DAC badges will provide free access to the Design Automation Conference exhibition and pavilion sessions.
The ESD Alliance is relaunching the annual panel session featuring CEOs from ARM, Cadence Design Systems, Mentor Graphics and Synopsys in Mountain View on April 9.
ARM and Tanner EDA aim to chart a path toward cheaper, easier to realize designs for the embedded and Internet-of-Things markets.
Implementation uses dedicated PULP technology in silicon for Green Waves Technologies on TSMC's 55nm LP process.
The Verification Futures conference organized by European EDA consultancy TV&S returns for its seventh year in early April with a focus on safety and security in the growing area of cyber-physical systems.
The Mentor Safe program aims to increase automotive users' confidence in tools and provide documentation needed for the functional safety standard.
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