EDA

July 17, 2014

Cadence brings FPGA prototyping and emulation into sync

Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
Article  |  Tags: , , ,   |  Organizations:
July 15, 2014

Cadence targets finFETs with RC extraction speedup

Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
July 10, 2014

Startup claims recipe for ultimate finFET

FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
Article  |  Tags: , , , ,   |  Organizations:
July 8, 2014

Focusing coverage for system-level integration

Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
July 4, 2014

Qualcomm takes 28nm to China in SMIC deal

Chinese foundry Semiconductor Manufacturing International Corporation (SMIC) is to get a helping hand to develop a production-class 28nm process from Qualcomm Technologies.
Article  |  Tags: , , , ,   |  Organizations: , ,
July 3, 2014

DVCon India heads to Bangalore

As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
Article  |  Tags: , , ,   |  Organizations:
July 2, 2014

OpenPDK accelerates design kit production at ST

STMicroelectronics is using the OpenPDK standard from Si2 to speed up the production and delivery of process design kits (PDKs) and asks for wider adoption by foundries.
June 25, 2014

Don’t just whine – it’s time for you to help shape DAC 2015

Any conference can only be as good as the feedback it gets. And next year's DAC team is actively looking for yours. It'll be worth your time.
Article  |  Tags: ,
June 25, 2014

Accellera releases version 1.2 of UVM

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
Article  |  Tags: , ,   |  Organizations: ,
June 20, 2014

14nm FD-SOI pushes strain and body bias for power savings

At the VLSI Technology Symposium a team led by STMicroelectronics described the techniques used for the upcoming 14nm FD-SOI to boost speed and density over the 28nm version.
Article  |  Tags: , , , , , , ,   |  Organizations: , ,

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors