Meridian Constraints update seeks to extend existing capabilities and address a gap not covered by other functional verification tools.
Ahead of June's Design Automation Conference, Agnisys and Semifore have both released tools aimed at reducing the overhead of implementing register-rich SoCs.
The company's annual 'What to see' list is now available for download and highlights some of EDA's less recognized areas of innovation.
Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
ARM says it has received test chips designed to check how well an SoC built around a 64bit multicore Cortex v8-A processor complex would work TSMC's upcoming 10nm FinFET process technology.
Videos detail techniques to improve the functional safety and reliability of FPGA designs, including the implementation of triple modular redundancy, safe FSM schemes and self monitoring.
Validating test patterns is a notoriously tricky and laborious process. Mentor Graphics has some new ideas on that front.
Companies presenting at User2User Santa Clara on April 26 include AMD, Microsoft, nVidia, Oracle, Qualcomm, and Samsung.
But project lead Chenming Hu, 'finFET's father', has also highlighted important changes in the funding landscape for university research.
Cadence Design Systems has made additions to its Virtuoso mixed-signal design environment intended to improve design for manufacture and the ability of teams to create and test safety-critical systems.
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