EDA

September 13, 2016

DVCon Europe to examine role of UVM, SystemC in system-level verification

DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Article  |  Tags: , , , ,   |  Organizations:
August 27, 2016

Creating a reference design flow for 10nm processes: video

Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Article  |  Tags: , ,   |  Organizations: ,
August 24, 2016

Cadence building photonics environment around Virtuoso

Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
Article  |  Tags: , ,   |  Organizations:
August 15, 2016

SystemC materials move to Apache 2.0 license

Accellera has moved to an Apache 2.0 open-source license for all of the supplementary materials for its SystemC library.
Article  |  Tags: ,   |  Organizations:
August 12, 2016

Chinese dates set for Asia-Pacific editions of Mentor Forum

Wally Rhines headlines as keynote at free technical events set for Shanghai on August 30 and Beijing on September 1.
Article  |  Tags: , ,   |  Organizations:
July 22, 2016

IEDM alters schedule to keep abreast of process updates

The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
Article  |  Tags: , , ,   |  Organizations:
June 20, 2016

Let’s lose the fins

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article  |  Tags: , , , , , ,   |  Organizations: ,
June 10, 2016

RC extraction from ‘virtual fab’ models may speed PDK availability

Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
Article  |  Tags: , ,   |  Organizations:
June 10, 2016

DFT to expand its role for long-term yield

Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
Article  |  Tags: , , , , ,   |  Organizations: , ,
June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
Article  |  Tags: , , , ,   |  Organizations:

PLATINUM SPONSORS

Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors