EDA

December 12, 2018

IEDM shows progress on embedded eMRAM

Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
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December 5, 2018

Leti takes the heat off monolithic 3D

CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
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November 30, 2018

Design Compiler updated for 5nm and beyond

Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
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November 27, 2018

Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results

Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
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November 14, 2018

Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm

Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
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November 13, 2018

Accellera updates UVM reference implementation

Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
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November 6, 2018

Netronome launches chiplet initiative for network-accelerator SIPs

Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
October 22, 2018

IEDM to examine scaling from multiple directions

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
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October 17, 2018

DVCon Europe takes in machine learning and stimulus for verification

Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.
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October 17, 2018

UltraSoC combines tools for cross-SoC debug and analysis

Following deals with Imperas and Percepio, UltraSoC has released an IDE aimed at debug, run control, performance tuning and runtime analytics for SoC development.
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