EDA

July 22, 2016

IEDM alters schedule to keep abreast of process updates

The International Electron Device Meeting has pushed back the deadline for its papers to get the latest developments in process and device design into the December conference.
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June 20, 2016

Let’s lose the fins

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
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June 10, 2016

RC extraction from ‘virtual fab’ models may speed PDK availability

Electrical analysis facility does RC extraction on virtual fab models, accelerating the availability of early PDKs for new processes
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June 10, 2016

DFT to expand its role for long-term yield

Design for test could look quite different in five years' time compared to the situation designers have today as chipmakers wrestle with the problems of yield control, safety, and aging.
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June 9, 2016

2D tools adapt to create smaller monolithic 3DIC designs

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.
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June 8, 2016

Minimize memory moves for greener data centers

Deep pipelines and dynamic memory sharing may provide the key to the development of faster and more efficient server-farm blades as the focus in hardware design moves to augmenting conventional processors with specialized accelerators.
June 7, 2016

ARM accelerates POP deployment for Cortex-A73

A faster implementation program for the POP support IP for ARM's cores has delivered a 16nm finFET package for the Cortex-A73 shortly after the core's Computex launch.
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June 7, 2016

Analyzer merges constraints for multiple timing modes

Ausdia has launched a product intended to reconcile the multiple sets of timing constraints needed for operating and test modes so that a consistent group of constraints can be fed to implementation tools.
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June 6, 2016

ARM recruits design houses and tools for quicker IoT projects

ARM aims to recruit more startups to develop IoT SoCs around the Cortex-M0 with design-house network and easier access to EDA tools.
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June 6, 2016

Intento uses graphs to optimize analog blocks

Startup launches an analog-circuit migration and optimization tool that uses less simulation time than traditional approaches the company claims.
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