Ceva has launched the fifth generation of its vision-oriented DSP core family with an architecture tuned for the fast-growing area of convolutional neural networks and deep learning.
UltraSoC plans to support the RISC-V open-source instruction architecture with its debug infrastructure and tools.
ARM has launched the first of its Cortex-R series of processors to be based on the v8R architecture, providing greater protection for software tasks from each other.
GlobalFoundries has introduced an embedded-MRAM option for its 22nm FD-SOI process: the 22FDX platform.
DVCon Europe this year provides a venue for extending UVM, SystemC and TLM for faster, more effective verification its organizing committee claims.
Ultra-low power security processor IP includes defences against side-channel attacks, data and instruction encryption, DSP options for sensor processing and more.
A look at some of trade-offs involved in building large system memories for enterprise equipment using DDR4 IP.
Synopsys video details challenges of 10nm design and its collaboration with Samsung Semiconductor to build a full flow to address them.
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
EEMBC has released version 2.0 of its suite for measuring the performance of automotive powertrain tasks on multicore processors.
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