Blog Topics

May 22, 2018

Arm Cortex-A processor team focuses on formal

Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
May 22, 2018

IEDM 2018 aims to span quantum, neuromorphic and CMOS devices

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
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May 11, 2018

Mixed-signal circuits push scaled CMOS at VLSI

The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
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May 9, 2018

Motion harvester wins MEMS design contest

Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
May 8, 2018

Cadence opens three fronts on mixed-signal failures

Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
May 4, 2018

7nm process with EUV to feature at VLSI

Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
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May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
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May 2, 2018

Arm adds tamper resistance to M-series core

Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
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May 2, 2018

User2User Silicon Valley rolls out later this month

Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
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May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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