The leading EDA analyst also charts growth for RTL and IC CAD in 2014 Market Share Summary, and highlights system-driven shifts in tool evaluation.
The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes - this time with finFETs.
Cadence has released a tool intended to ease the creation of scenario-driven tests to better exercise complex IP and SoC designs.
In a presentation at the recent ARM TechCon, HiSilicon described the issues in putting together a 16nm finFET-based design built around a cluster of ARM’s Cortex A57 processors.
Canadian startup Invionics has launched a development environment and packager intended to make it easier for users within chipmakers and design houses to build customized tools.
TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.
Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
UK-based RAL Space has picked up an award from National Instruments for a system the organization built to test a pair of cameras ahead of being being deployed on the International Space Station to photograph the Earth from orbit.
Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
Siemens has developed an open-source implementation of the Multicore Association's MTAPI to make it easier to divide and manage concurrent tasks that run on systems with multiple processors.
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