Cadence has use physically aware placement in a test tool that promises less routing congestion for scan test and which increases the potential for stimulus compression.
The Multicore Association has started work on standardizing a set of APIs that aim to simplify communications between processors in heterogeneous multicore SoCs
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
The Qt Company has changed the licenses it supports on the open-source versions of its user-interface software framework, removing the LGPL2.1 version.
The Prpl Foundation has published a guide to techniques it claims will improve the security of embedded systems.
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Cortus has added to its version 2 architecture a processor core that offers hardware support for floating-point code.
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
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