Blog Topics

November 18, 2014

Startup builds environment for custom EDA tools

Canadian startup Invionics has launched a development environment and packager intended to make it easier for users within chipmakers and design houses to build customized tools.
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November 12, 2014

TSMC begins risk production of 16FF+

TSMC says it has begun risk production on its FinFET Plus (16FF+) process, claiming that it has reached a greater level of maturity earlier in its development cycle than previous nodes developed at the foundry.
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November 12, 2014

Chip tariff eliminated and the big winner is… China?

Not just Intel and TI but also Lenovo and Huawei have cause to welcome end to 25% import tax. And could it even help reinvigorate Chinese start ups?
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November 11, 2014

Space camera project uses rapid development for test

UK-based RAL Space has picked up an award from National Instruments for a system the organization built to test a pair of cameras ahead of being being deployed on the International Space Station to photograph the Earth from orbit.
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November 4, 2014

From Darwin to Mao: how multi-patterning could move up the flow

Are we torn between evolution and revolution? Mentor Graphics' Joe Sawicki discusses how pattern matching already in fabs could move up and radically alter the design flow.
October 31, 2014

Siemens produces open-source code for multicore acceleration

Siemens has developed an open-source implementation of the Multicore Association's MTAPI to make it easier to divide and manage concurrent tasks that run on systems with multiple processors.
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October 29, 2014

Mentor now scales Xpedition’s multi-board PCB capabilities

The latest update to Mentor's market-leading PCB design suite aims to unify system definitions across multiple tools to reduce errors.
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October 28, 2014

10Gbit/s USB 3.1 IP and verification support on the way

USB 3.1 IP, verification IP, virtual development kit build on Synopsys' USB 3.0 DesignWare and supporting ecosystem
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October 28, 2014

Cadence tool automates library creation of analog macros

Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.
October 22, 2014

Cadence targets ISO 26262 with verification support

Cadence Design Systems has built a verification environment around its vManager software for ICs and systems that need to conform to the ISO 26262 safety standard.

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