Blog Topics

March 26, 2015

Xmos brings programmable networking to Gigabit Ethernet

Xmos has launched a series of microcontrollers based on its timesliced multicore architecture that adds Gigabit Ethernet interfaces.
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March 24, 2015

DAC 52 keynotes focus on body-worn electronics and vehicle design

The 2015 Design Automation Conference in San Francisco will feature keynotes that focus on body-worn electronics such as Google’s Smart Contact Lens and automotive issues.
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March 24, 2015

TI uses Cortex-M4F to provide low-power 32bit upgrade for MSP430

Texas Instruments has launched a family of ARM-based microcontrollers intended to act as a migration path from its low-energy 16bit MSP430 series, developing its own flash-capable 90nm process to implement them.
March 24, 2015

Mentor unites chip-to-package flow with Xpedition Package Integrator

Flow draws on existing strengths in Xpedition, Valor, Nimbic and Flotherm among others to optimize 3D design projects and improve cross-disciplinary communication.
March 18, 2015

ARM and Cadence agree to share IP access

ARM and Cadence have signed a deal that provides the IP teams at both companies with access to each other's cores.
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March 17, 2015

China’s foundry outlook improves but still much to do

Foundry veteran Simon Yang told Semicon China while things are looking up the country cannot count on ‘traditional’ methods or advantages if it's to be a major chipmaker.
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March 12, 2015

Cea-Leti opens FD-SOI design center

CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process.
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March 11, 2015

IoT and RF ‘to drive FD-SOI adoption’

The FD-SOI technology developed by CEA-Leti and STMicroelectronics is beginning to gain ground as chipmakers investigate the process as a way to deliver low-energy, wireless-capable SoCs.
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March 11, 2015

Charting out the roadmap for FD-SOI

As plans crystallize to take FD-SOI down to 10nm, CEA-Leti argues that the technology can provide an alternative path to that of finFETs to get to 7nm processes and beyond.
March 10, 2015

Cadence reworks implementation for both finFET and older processes

Cadence Design Systems has coupled the parallel-processing techniques behind its recently launched sign-off tools to engines intended to deal with sub-28nm process issues in a suite that reworks the company’s key implementation tools.
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