Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.
New flow enables high-performance, high-integration designs.
Arm aims to bring protection against physical tampering and side-channel attacks into processor cores designed for IoT nodes, starting with one of its M-series designs.
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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