Cadence Design Systems has developed an FPGA-based prototyping system that takes advantage of much closer alignment with its existing Palladium XP emulator to accelerate bring-up and support debugging across both platforms.
As heterogeneous multicore SoCs move into the mainstream, embedded developers face increasing integration and debug challenges.
Cadence has launched a parasitic-extraction tool that takes better advantage of multiple computers and which has been certified for TSMC's 16nm finFET process.
FinScale has developed a design and process recipe for a finFET structure that the company claims is easier to make but which provides better performance than existing approaches.
With an eye on the markets for wearables and the internet of things (IoT), digital signal processing specialist IP company CEVA has bought RivieraWaves, a France-based supplier of WiFi and Bluetooth cores, in a deal worth an expected $19m.
Mentor Graphics has expanded its portfolio of tools and software for the automotive market with its second acquisition of the year in this sector.
Coverage and hardware acceleration can bring greater focus to the SoC-level checks needed to ensure that the final silicon works as expected – both issues tackled in an archived Cadence webinar.
Chinese foundry Semiconductor Manufacturing International Corporation (SMIC) is to get a helping hand to develop a production-class 28nm process from Qualcomm Technologies.
The International Energy Agency (IEA) has turned its attention to slashing the electricity demands of network-attached devices with a report that says manufacturers and service providers need to look at changes to protocols and features such as energy harvesting.
As well as starting up a version for the European market, the Accellera Systems Initiative is taking DVCon to India in the early autumn.
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