Blog Topics

January 18, 2017

Wafer expansion hits the buffers

What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.
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January 17, 2017

DesignCon 2017 preview: Mentor Graphics

DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
January 9, 2017

VLSI Symposia issue calls for papers

Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
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December 22, 2016

Webinar discusses SoC security, area, and power trade-offs

SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
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December 19, 2016

White paper discusses optimising the efficiency of DDR memory subsystems

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.
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December 15, 2016

Benchmark effort to look at IoT security performance

EEMBC has launched a benchmarking effort to test the performance of security and crypto-functions on embedded devices.
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December 12, 2016

IEDM explores faces of 3D monolithic integration

What will 3D integration look like? IEDM 2016 explored some of the options ranging from IoT sensors to advanced logic.
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December 7, 2016

IMEC stacks nanowire transistors together on CMOS

IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
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December 7, 2016

Overcoming electromigration analysis limitations for larger on-die power grids

Award-winning paper describes new strategy offering both greater speed and accuracy.
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December 7, 2016

HiSilicon licenses onchip debug engine for SOCs

HiSilicon has licensed UltraSoC’s semiconductor IP to build into SoCs for system monitoring, analysis, and optimization.
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