Early registration has opened for the DVCon Europe conference to be held in Munich, Germany in November.
Rapid virtual prototyping and a metal stack that's more designer friendly are two of the ways in which Samsung aims to build up foundry market share for its 14nm and 10nm finFET processes.
The need for virtual prototyping at the PCB-design has led to changes in the way PSpice is being used – with much greater emphasis on cosimulation.
GlobalFoundries has developed variants of the 28nm FD-SOI process that offer smaller die sizes and lower-power operation.
IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
The leading EDA analyst passed away late last week after a short illness. Graham Bell offers this remembrance.
Companies such as Broadcom are experiencing threefold test-pattern reductions through the use of automatically inserted gates that allow parallel cones to share the same ATPG patterns that would not be possible using conventional test generation schemes.
The latest update to the CustomSim FastSpice tool from Synopsys provides more consistent speedups from multicore workstations and adds support for BCD processes and real-number modeling.
Research by Professor John Rogers' group at the University of Illinois is leading to biodegradable electronics, for both defense and medical applications.
Foundry claims isolation and device integration advantages for 180nm SOI process, help to absorb extra costs of SOI wafers
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