Volume 5

June 1, 2008

Using Open Virtual Platforms to build, simulate and debug multiprocessor SoCs

The Open Virtual Platforms (OVP) initiative aims to help resolve the difficulties that arise today when modeling multicore systems-on-chip (SoC) so that designers can perform early and timely test of the embedded software that will run on the end devices. As architects continue to add more cores to meet hardware design goals, the complexity of […]

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June 1, 2008

Systems design automation for real

The Design Automation and Test in Europe (DATE) conference is a comparatively young event—it reached only its 11th edition this March. Nevertheless, it has now firmly established itself on the EDA calendar and this year significantly extended its scope to become the world’s most important electronic systems design automation conference. At the same time, it […]

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June 1, 2008

STIX to the task

Before 2001’s historic downturn, the semiconductor industry was primarily driven by the corporate and enterprise markets. This bias led to a somewhat predictable three-year business cycle of peaks and troughs. Corporate buying practices, technology requirements and IT replacement policies are all relatively easy to predict—right down to the nature of the semiconductors that underpin the […]

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March 1, 2008

The veteran competitor

In his early days in the semiconductor industry, Morris Chang Morris Chang was one of the “non-Texans” to Texas Instruments and was a manager struggling with the question of how to get individual transistor yields to somewhere around three or even four per cent. One of his colleagues – another immigrant to the Lone Star […]

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March 1, 2008

The European view

This year’s general chair of Design Automation and Test in Europe is Donatella Sciuto, a full professor at the Politecnico d iMilano in Milan, Italy. She received her Laurea in Electronic Engineering from the Politecnico di Milano in 1984 and her PhD in Electrical and Computer Engineering in 1988 from the University of Colorado, Boulder. […]

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March 1, 2008

Parasitics: an old problem reaches new heights

The semiconductor industry faces increasing challenges in the design of complex systems-on-chip, and while some have sprung from new, only recently anticipated sources, others are, in fact, very familiar. Foremost among these are the interconnect delays caused by the increasing influence of parasitic networks. Parasitic inductance is also a growing concern. The causes of parasitic […]

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March 1, 2008

How VHDL designers can exploit SystemVerilog

SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features. Anyone involved in systemon- chip (SoC) design may face a mixed-language environment and will appreciate being able to leverage SystemVerilog with the VHDL portions of […]

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March 1, 2008

High quality scan test with minimal pins

Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]

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March 1, 2008

ESL at the inflection point

Electronic system level (ESL) design is moving to a new stage in its development, advancing from a proof-of-concept environment to one that is seeing its adoption and deployment at the forefront of design. The article terms this shift ‘ESL 2.0’. The reason for this goes beyond mere marketing hype. Inherent in the transition defined above […]

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March 1, 2008

Efficient packet header parsing using an embedded configurable packet engine

Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For […]

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