Volume 5

September 1, 2008

Planting seeds

The 17th annual PCB West Conference and Exhibition takes place this year at the Santa Clara Marriott, September 14-19. For 2008, the conference’s theme is “Grow your knowledge in the heart of Silicon Valley.” This is an approach intended to reflect some of the obvious hot button issues in board design (e.g., high-speed, lead-free, etc.) […]

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September 1, 2008

An industry-as-laboratory approach to dependability for high-tech systems

The dependability of high-volume embedded systems, such as consumer electronics devices, is threatened by a combination of rapidly increasing complexity, decreasing time-to-market, and strong cost constraints. This environment poses challenging research questions that are being investigated in the Trader Project, following an industryas- laboratory approach. This paper describes the vision behind the project and reviews […]

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September 1, 2008

Building reusable verification environments with OVM

This article reviews the reuse potential within the Open Verification Methodology, with special focus on four particularly fruitful areas: testbench architecture, testbench configuration control, sequences, and class factories.
September 1, 2008

Benchmarking the network-on-chip

From its inception, the OCP standard was designed to address the advent of heterogeneous processors and multicore SoC development. Since the OCP-IP organization opened for business in December 2001, it has established eight technical working groups (WGs) to develop tools, technologies and products that support the standard, leading in turn to the release of a […]

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September 1, 2008

Rapid prototyping for the 802.11 era

The 802.11 family of wireless local area network (WLAN) standards is becoming ubiquitous. Products for its various fl avors – up to and including its latest 802.11n incarnation – must reach the market as quickly as possible. This implies a need for rapid prototyping, typically on an FPGA platform. This article describes how the design […]

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September 1, 2008

Product development efficiency through ECAD-MCAD collaboration

In May 2008, the ProSTEP iViP Association released an agreed data schema and communication protocol to enhance collaboration between electrical and mechanical CAD tools (ProSTEP iViP Recommendation ECAD/MCAD, PSI 5). The article sets out the need for the new standards and how they deliver greater design effi ciencies than existing technologies, such as the IDF […]

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September 1, 2008

Parallel programming for realists

Sharing industry-driven best practices in parallel programming is the only way to unlock the benefits of efficient use of multicore silicon platforms and dramatically increase their rate of adoption. It is now widely agreed that the largest single brake on the adoption rate for multicore platforms is the ability of software developers to program them. […]

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September 1, 2008

Now this is a tough one

For the sake of clarity and sanity, let me first point out that you are reading an article written in the fall of 2008. The importance of this will become obvious when I reveal my topic: parallel programming for the multicore age. You thought I was about to claim first-past-the-post on a new technological challenge […]

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September 1, 2008

Modeling embedded systems using SystemC extensions

SystemC AMS extensions introduce new language constructs for the design of embedded analog/mixed-signal systems. This paper presents the novel modeling language for analog and mixed-signal functions that supports design and modeling of telecommunications, automotive and imaging sensor applications at various levels of abstraction. A simple example illustrates how new features facilitate a design refinement methodology […]

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September 1, 2008

Clock domain crossing: guidelines for design and verification success

Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains: register the signal in the sending clock domain to remove combinational settling; and synchronize the signal into the receiving clock domain. […]

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