Volume 4

September 1, 2007

Characterizing process variation in nanometer CMOS

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. This paper presents an overview of test structures for characterizing statistical variation of process parameters. It discusses the test structure design and characterization strategy for calibrating random […]

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September 1, 2007

Changing the economics of chip verification

Introduction Burgeoning design complexity has greatly increased the scale of the verification effort. At the same time, there is a widening gap between the growth in vital activities such as functional verification and the ability of tools and methodologies to fulfill such tasks efficiently. If we fail to close that gap, the potential impact on […]

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June 1, 2007

Share and share alike

For a design targeted at the 130nm process node or below, the cost of a dedicated mask-set is getting brutal. At 130nm itself, a semiconductor company is likely to pay between $500,000 and $600,000 per set. That price tag rises to around $1m at 90nm, and to $1.5m at 65nm(Figure 2). One recent forecast for […]

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June 1, 2007

Shadow model and coverage driven processor verification using SystemVerilog

This paper describes a random test generation strategy we are using to complement the verification of upcoming generations of processor. SystemVerilog provided the means to define the functional coverage of our design and to employ the shadow modeling technique, significantly improving our verification flow. Shadow modeling is a reliable method for proving the functionality of […]

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June 1, 2007

Optimizing energy in processor-memory subsystems during SoC design

System-level architectural decisions made before any RTL code has been written have a much larger impact on overall system energy than RTL-level, gate-level, or circuit-level tweaks. The Xenergy tool from Tensilica estimates energy for a processor subsystem (processor, caches, local memories) based on the application code that will run on that subsystem. Designers can thus […]

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June 1, 2007

New breed of SPYDER discovered

Freescale Semiconductor manufactures some of the industry’s most widely used microcontrollers. The article describes the functionality behind the new Background Debug Module that has been developed for its 8 and 16bit MCUs. The BDM provides all that is needed to write, compile, download, in-circuit emulate and debug code, when deployed in conjunction with the well-known […]

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June 1, 2007

Implementation of a DFM checker for 65nm and beyond

Design for manufacturing (DFM) sign-off is a required step in most deep sub-micron technology design environments. However, there is no common methodology for DFM sign-off. We believe DFM should not only give an estimate of the yield, but should also point out where failures are most likely to occur, and where designers can improve their […]

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June 1, 2007

Start Here

You see, I feel a bit like Columbo. No, my raincoat is not egregiously grubby and I did recently buy a new car, but, well, “Dere’s still one thing dat bothers me.” And it’s this: where is the semiconductor industry going in terms of the placement of risk and capital in the value chain? Let […]

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June 1, 2007

DAC past, present and future

When I left the semiconductor industry to become an EDA Analyst, I was struck by two things. The first was the professionalism of the PR firms handling the EDA accounts. They not only did jobs that would be expected of them by silicon vendors, but also performed functions that we would consider part of a […]

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June 1, 2007

Broaden your perspective

Some 161 papers will feature during this year’s 44th Design Automation Conference (June 4-8) in San Diego with four strands at the forefront. System-level design (ESL), design for manufacturing/yield (DFM/DFY), low-power design and verification accounted for more than 40% of submissions this year, and the final line-up represents these topics in broadly similar proportion. For […]

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