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March 15, 2017
DVCon China takes place at the Parkyard Hotel, Shanghai on April 19th.

DVCon中国将于4月在上海亮相

DVCon中国大会主席刘红亮讨论了Accellera新增的DVCon中国ASIC设计和验证会议的看点。
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December 7, 2016
David Wiens is Business Development Manager for the System Design Division at Mentor Graphics.

Tackling the multi-board reality of systems of systems

We talk to Mentor's David Wiens about how the company is giving the board-to-factory design flow a needed upgrade.
October 14, 2016
networking-soc-mentor-ixia-featim

Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
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May 13, 2016
Jenkins automation server logo

How continuous integration with Jenkins serves verification flows

A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
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March 21, 2016
featimrtlsynth

How to maximize productivity with faster, high-capacity RTL synthesis

New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
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January 13, 2015
Sarath Kirihennedige, Real Intent

Taking control of constraints verification

Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
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October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
July 22, 2014
The evolution of software debug using hardware emulation

The evolution of software debug using hardware emulators

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
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December 23, 2013
Featured image Marvell case study

Better management of timing closure and optimization

How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
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