We talk to Mentor's David Wiens about how the company is giving the board-to-factory design flow a needed upgrade.
How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
A technique built for software development is now helping hardware engineers master increasingly complex verification flows.
New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR
Constraints are a vital part of IC design, yet the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.
This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
How Marvell used an enhanced ECO tool flow for SoC design to cut overall time-to-timing-closure by nearly 70%.
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