IP Topics

August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
July 19, 2013
Cisco switch chip layout detail

Eliminating iterations in gigahertz ASIC handoff

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
Article  |  Tags: , , , ,   |  Organizations: ,
July 3, 2013
Graham Bell, RealIntent

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
Expert Insight  |  Tags: , ,   |  Organizations:
May 30, 2013
Neel Desai, Synopsys

Enabling greater productivity and schedule predictability in IC design

How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
Expert Insight  |  Tags: , , ,
May 23, 2013
Cost of verification

Facing the verification management challenge

The growing verification challenge, and how to address it by coordinating multiple debug strategies.
May 14, 2013
Graham Bell, RealIntent

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
April 24, 2013
Mick Posner, Director of Product Marketing for Synopsys' FPGA-Based Prototyping Solutions.

IP-to-SoC prototyping demands consistency

Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.
Expert Insight  |  Tags: , ,   |  Organizations: ,
April 4, 2013
Michael Sanie, Synopsys

Debugging the debug challenge

Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
April 1, 2013

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
Article  |  Tags: , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors