Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
The encryption chain for today's highly collaborative designs needs to be managed with care.
Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
How the HPC company used Synopsys' Lynx Design System to standardise its flow and simplify migration to the next node.
How to speed project start-up, boost designer productivity and increase schedule predictability using design management tools.
The growing verification challenge, and how to address it by coordinating multiple debug strategies.
Debug of logic and testbench debug makes up 35% of chip design, and is growing as power-management and hardware/software issues become part of the task.
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