Design Management

October 8, 2015
Amol Herlekar, Synopsys

Preparing for low-power verification success: setting objectives and measuring outcomes

A look at what it takes to verify low-power SoC designs, including setting objectives and measuring outcomes in a UPF-driven verification strategy
Expert Insight  |  Tags: , ,   |  Organizations: ,
August 24, 2015
Warren Kurisu is the Director of Product Management in the Mentor Graphics Embedded Systems Division, overseeing the embedded runtime platform business for the Nucleus RTOS, Mentor Embedded Linux, virtualization and multicore technologies, and graphics and development tools. Warren has spent nearly 30 years in the embedded industry, both as an embedded developer and as a business executive.

A scalable RTOS and other essentials for embedded wearables development

The wearables market is booming. Successful development depends on assembling the right software and hardware tools. Here's a primer on what to look for.
June 25, 2015
Agile diag 2 featimg

Applying agile techniques to IC design

How agile methodologies can be applied to personal and team practice in IC design, including for developing cloud accelerators at Microsoft
Expert Insight  |  Tags: ,   |  Organizations: , , , , , ,
February 27, 2015
IP based design with Synplify - featimg

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Article  |  Tags: , , , , ,   |  Organizations:
January 20, 2015
Veloce2 emulator

Assertion-based emulation

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
November 5, 2014
Pattern matching DRC featured image

How to use pattern matching to improve automatic waiver management

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
Article  |  Tags: , , ,   |  Organizations:
July 25, 2014
Steven Cline is a senior design automation Manager at Altera’s Austin Technology Center, focusing on design-flow automation for traditionally placed and routed blocks and custom FPGA IP used on Altera’s advanced FPGA products.

Using standardized design flows to cut time to tape-out – and speed design-flow evolution

Altera uses standardized design flows to help integrate Intel foundry rules, cut time to tape-out - and speed the evolution of its design flows.
Expert Insight  |  Tags: , , , ,   |  Organizations: , ,
April 28, 2014
John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
Expert Insight  |  Tags: , , ,   |  Organizations: ,
April 22, 2014
Tech Design Forum Synopsys - semtech - featimg

Accelerating multi-corner multi-mode sign-off using the Lynx Design System

Mixed-signal chip designer Semtech on using Lynx Design System to manage multi-corner multi-mode sign-off when you've got 306 scenarios to check.
Article  |  Tags: , , , ,   |  Organizations:
April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.


Mentor Graphics GLOBALFOUNDRIES Synopsys Samsung Semiconductor Cadence Design Systems
View All Sponsors