Assembly & Integration

September 16, 2013

The USB 3.0 Link Layer

A look at the way in which the USB 3.0 Link Layer manages the port-to-port flow of data between the host and the device.
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September 16, 2013

USB 3.0 system overview

An overview of the USB 3.0 architecture, covering the USB Host, USB Device(s) and USB Interconnect, as well as the related receptacles, plugs and cables.
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September 16, 2013

USB 3.0 protocol layer – part 1

A first look at the role of the protocol layer in USB 3.0.
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September 16, 2013

The USB 3.0 Functional Layer

A look at the USB 3.0 functional layer, an application layer and system software on the host side, and a logical function and device on the device side.
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September 16, 2013

USB 3.0 protocol layer – part 2

A look at the role of four types of transaction in the USB 3.0 protocol layer: bulk, control, interrupt and isochronous.
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September 16, 2013

The USB 3.0 Physical Layer

A look at the USB 3.0 physical layer, including the PHY and the physical connection between two ports, which is carried on two differential data pairs.
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August 25, 2013
Tim Whitfield, director of engineering, ARM Taiwan

Proving the 20nm ecosystem with the ARM Mali GPU

What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
July 25, 2013
Dam Benua, Synopsys

Formal techniques tackle the SoC verification challenge

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
July 19, 2013
Cisco switch chip layout detail

Eliminating iterations in gigahertz ASIC handoff

How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
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July 3, 2013
Graham Bell, RealIntent

The challenge of clock domain crossings – and some solutions

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
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