Assembly & Integration

February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
February 10, 2016
Geoffrey Ying, director of product marketing, AMS group, Synopsys

Speeding AMS verification by easing simulation debug and analysis

How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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January 12, 2016
Angela Raucher is product line manager for Synopsys’ ARC EM processors.

Processor configuration for low-power IoT applications

Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
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January 11, 2016

FPGA design for functional safety

Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
September 18, 2015
Featured image: PHY VIP Sep 15

How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
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May 6, 2015

Fixing late ECOs in ARM core subsystems at STMicroelectronics

Using equivalence checking to validate ECOs in ARM core subsystem development at STMicroelectronics
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April 20, 2015

Developing and integrating configurable GPU IP using FPGA-based prototyping

How Imagination Technologies used FPGA-based prototyping to develop its GPU IP and integrate it into a real world system
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February 27, 2015

Getting the most out of IP based FPGA design with Synplify

How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
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January 7, 2015

A holistic approach to IoT chip design

A look at the challenges of designing chips for the Internet of Things, or IoT, and some of the responses to those challenges
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November 5, 2014
Pattern matching DRC featured image

How to use pattern matching to improve automatic waiver management

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
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