Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
A look at the ways in which the evolving MIPI standard is being used to provide connectivity in automotive, mobile, multimedia, virtual reality, augmented reality and related applications.
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
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