Assembly & Integration

December 2, 2016
Synopsys Diagram2

Hierarchical signoff of SoC designs at advanced process nodes

Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
November 10, 2016
tdf_new-uses-for-mipi-interfaces-featimg

The advantages of MIPI specifications in mobile, automotive and multimedia applications

A look at the ways in which the evolving MIPI standard is being used to provide connectivity in automotive, mobile, multimedia, virtual reality, augmented reality and related applications.
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October 3, 2016
Dr Walden Rhines is Chairman and CEO of Mentor Graphics

Wally Rhines separates the signal from the noise

Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
September 9, 2016
Jean-Marie Brunet is Senior Director of Marketing for the Emulation Division at Mentor Graphics.

The inside track on emulation growth

Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
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August 18, 2016
A73 core performance vs process

Challenges of tool, process and design collaboration at advanced nodes

A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.
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June 1, 2016
How Google and Qualcomm use HLS and HLV

How Google and Qualcomm exploit real world HLS and HLV

By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
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May 10, 2016
USB Type C connector

Implementing USB Type-C

A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
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March 3, 2016
Whats cooking at the Flash Diner - verification IP

What’s cooking at the Flash Diner?

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
February 22, 2016
ICCII floorplanning article - featimg

Floorplanning complex SoCs with multiple levels of physical hierarchy

How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
February 18, 2016
RTL Floorplanning - Featured Image

How new RTL floorplanning techniques speed physical design

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.

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