High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
The MIPI RFFE standard provides a common approach to controlling power amplifiers, low-noise amplifiers, filters, switches, power management modules, antenna tuners and sensors in SoCs and systems.
The USB Type-C connector is versatile and already gaining traction in laptops, tablets and desktops. Here's how verification IP plays an important role in achieving the best implementation.
To check the connectivity of an SoC, first you have to define what a connection is...
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
A look at the ways in which the evolving MIPI standard is being used to provide connectivity in automotive, mobile, multimedia, virtual reality, augmented reality and related applications.
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
Analysts say there is a $1B market on the horizon. We talk with Mentor's Jean-Marie Brunet about where such a number could come from.
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