A look at how collaboration between design, process and tool development is becoming increasingly important to get the best out of the most advanced nodes.
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
Many IoT applications have a very strict energy budget. SoC designers targeting the IoT have to trade off providing the features that the market demands with the power budget the applications demand. What are their options?
Using triple modular redundancy, error detection and correction, and 'safe' FSMs to ensure greater functional safety in FPGA-based designs
Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
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