Exploring the tradeoffs between implementing DDR4 and HBM for high-bandwidth memory subsystems.
The challenge for designers is to find ways of providing high levels of security in low-cost devices that have become worthwhile targets because of their role as gateways to more valuable information.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
Using deep learning techniques and convolutional neural networks to bring facial recognition capabilities to embedded systems.
Addressing the challenge of achieving ASIL D certification of the functional safety of an SoC for use in the safety-critical path of an automotive system.
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