September 28, 2015
HAPS cables 150

FPGA-based prototyping 2: Understand the real cost

Part two of our series on FPGA-based prototyping looks at two critical factors to address before a project begins: budgeting and high-level implementation.
September 23, 2015

Mounting Fiji: How AMD realized the first volume interposer

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?
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November 6, 2014
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 28, 2014
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Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
October 10, 2014
Dr Yervant Zorian, Synopsys

Finding and fixing faults in finFET memories

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
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August 29, 2014
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Exploiting Verific tools and features at the right abstraction level

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
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May 14, 2013
Graham Bell, RealIntent

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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November 5, 2012
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20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
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August 18, 2012

When good DFT goes bad: debugging broken scan chains

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
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