DFT

October 14, 2017
Michael Chen is Director, Design for Security, in the New Ventures Division of Mentor, a Siemens Business.

Making security a profit center for silicon

The assumption has been that extra security eats into profit margins. But with some lateral thinking it can actually improve the bottom line.
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September 21, 2017
Diagnosis-driven yield analysis featured image

Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
May 8, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part One: Mentor as a Siemens business

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
April 10, 2017
Ron Press is a technical marketing director at Mentor - A Siemens Business. He specializes in DFT and BIST and was the 2010 General Chair of the International Test Conference.

Drawing on hierarchical DFT to benefit all designs and flows

Hierarchical DFT is vital for large, complex designs. Users still to transition to the technique can nevertheless exploit its pattern reuse strategies as they move toward adoption.
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January 16, 2017
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An ISO 26262 approach to meeting the cost, quality, reliability, and integration needs of automotive ICs

Meeting ISO 26262 standards for automotive safety means applying a consistent approach throughout the design process. Here's how to start.
January 10, 2017
Silicon bring-up Tessent

Accelerate silicon bring-up in a bench-top environment

How a new software-led flow speeds silicon bring-up within the Tessent environment, including a Cypress Semiconductor case study.
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November 8, 2016
Technical feature on scan pattern best practice

Best practice in scan pattern ordering for test and diagnosis

How to tune your scan pattern creation and application to cost-effectively match your test objectives.
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October 14, 2016
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Taking risk out of software-driven networking SoCs

How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
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December 29, 2015
Stephen Pateras

Memory BIST for automotive designs

Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
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November 6, 2015
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Reducing test costs through multisite and concurrent testing

How to save test time and test costs by doing more tests in parallel, increasing compression, pooling tester memory, managing branching - and more
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