DFT

August 29, 2014
Verific Featured Image

Exploiting Verific tools and features at the right abstraction level

EDA vendors and internal CAD teams use Verific parsers for tool development. Here's how one company developed its strategy for this popular technology.
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May 14, 2013
Graham Bell, RealIntent

Building an RTL sign-off flow

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
November 16, 2012
Stephen Pateras

IJTAG: delivering an industry platform for IP test and integration

Mentor's Stephen Pateras explains how the proposed IJTAG standard speeds IP test by replacing time-consuming custom and ad hoc methodologies.
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November 5, 2012
20nm test feature image

20nm test demands new design-for-test and diagnostic strategies

20nm test needs new approaches to cope with short delay defects, new memory failure mechanisms and the consequences of test compression strategies
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August 18, 2012

When good DFT goes bad: debugging broken scan chains

Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
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July 11, 2012
tdf-jul12-mentor-ijtag-feat

Welcome to IJTAG: a no-risk path to IEEE P1687

Making a smooth transition to IJTAG, the scan-test strategy for IP blocks, without having to change your existing hardware.
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July 3, 2012
Juergen Schloeffel

Why cell-aware testing is important

Characterizing standard-cell defect mechanisms helps improve IC testing
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January 24, 2012

Design for test: a chip-level problem

The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.
August 23, 2011
tdf1109_kilopass1_medium

Ensuring the reliability of non-volatile memory in SoC designs

This article describes various non-volatile memory (NVM) intellectual property (IP) alternatives with specific reference to their integration within system-on-chip designs targeting the 65nm process node and below. The article considers many of the strengths and vulnerabilities of these IP options, and then describes the tests that must be undertaken to ensure their long-term reliability, particularly [...]
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August 23, 2011

The testiest place on earth

But in a good way. As ITC moves to Anaheim’s Disneyland in September, we preview the 2011 edition.
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