For the sake of clarity and sanity, let me first point out that you are reading an article written in the fall of 2008. The importance of this will become obvious when I reveal my topic: parallel programming for the multicore age. You thought I was about to claim first-past-the-post on a new technological challenge […]
The 802.11 family of wireless local area network (WLAN) standards is becoming ubiquitous. Products for its various fl avors – up to and including its latest 802.11n incarnation – must reach the market as quickly as possible. This implies a need for rapid prototyping, typically on an FPGA platform. This article describes how the design […]
UK-based analyst group Future Horizons has been organizing its international electronics forums for 17 years and they continue to provide an invaluable look into what the industry’s top tier of managers is thinking. It is one thing to get your own wise analysts to pronounce on tomorrow’s market, but it is something else entirely to […]
From its inception, the OCP standard was designed to address the advent of heterogeneous processors and multicore SoC development. Since the OCP-IP organization opened for business in December 2001, it has established eight technical working groups (WGs) to develop tools, technologies and products that support the standard, leading in turn to the release of a […]
Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains: register the signal in the sending clock domain to remove combinational settling; and synchronize the signal into the receiving clock domain. […]
Justin Rattner will this year mark 35 years with Intel. His career with the technology giant has seen him collect numerous accolades, particularly for work in areas such as high performance computing (HPC). He was Intel’s first principal engineer and was its fourth member of staff to be named a fellow (he is today a […]
Electronic system level (ESL) is typically defined as design above the register transfer level (RTL). When applied to hardware design, ESL is the process of describing hardware functionality at higher levels of abstraction to increase designer productivity and enable greater degrees of exploration. With ESL, hardware designers no longer spend most of their time designing […]
The paper describes some of the main challenges in the latest process shrink for the Cell Broadband Engine, developed jointly by IBM, Sony and Toshiba. The authors show how the move from a 65nm to a 45nm SOI process was achieved by concentrating on four primary goals: automating the migration; setting a 30% power reduction […]
Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]
