Silicon photonics verification: Progress through adaptation
SiP promises advances in transmission speeds, bandwidth, accuracy and low power but verification requires careful evolution of existing tools.
EDA Topics
Making sense of cloud EDA
How to carry out a sensible analysis of cloud EDA's potential, so you get the right tools and computational resources to deliver increasingly complex designs.
Use machine learning and visualization to accelerate Liberty file verification
Learn how to bring together your NLDM and CCS models to reach timing closure faster with Solido Analytics.
Out-of-sync data issues in parallel design flows need automated design integrity checks
Overcome problems created by mismatches between library exchange format (LEF) and GDS or OASIS representations to avoid design delays.
How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
How automated static checks help verify complex circuits for better performance and reliability
Learn how power-intent, LDEs, ESD and voltage-aware spacing techniques can particularly benefit from the use of static verification checks.
DVCon Europe best paper assesses clock design
The best paper at DVCon Europe 2020 analyzed different multiclock strategies for SoCs for their power and flexibility
Spiral in on silicon bugs in six formal steps
The best paper winner at DVCon 2021 details a comprehensive methodology for making the best use of formal verification for bug hunting
The path to full functional monitoring
Joe Sawicki of Siemens EDA recently addressed the main trends in design delivery from architecture to validation to digital twins - and where they may soon take the industry and its products.
Silicon lifecycle solutions help you listen to your chip
SLS brings the power of product lifecycle management to the increasingly complex oversight challenges in electronic systems design.
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