IC Implementation

May 29, 2014
Near-threshold computing for minimum energy - thumbnail

Near-threshold and subthreshold logic

By taking the circuit supply voltage close to that of the threshold voltage or even below, it is possible to optimize low-power VLSI design. But there are pitfalls.
May 26, 2014

Design for security

Design for security is an emerging topic in hardware engineering demanding a more holistic approach that traditional cryptographic implementation.
May 24, 2014
Dopant-level trojan standard cell developed by Georg Becker and coworkers

Hardware trojan attacks and countermeasures

IC designers are becoming increasingly worried about the possibility of third parties inserting malicious 'trojan' circuitry into their ICs.
May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
May 19, 2014

10nm processes

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.
May 19, 2014

14nm/16nm processes

The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
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April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
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February 11, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.

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