IC Implementation

May 19, 2014

On-chip clock strategies and GALS

The increased use of IP and a rise in process variability is driving a move to look at alternatives to traditional low-skew clock distribution strategies.
May 19, 2014

10nm processes

The 10nm generation is the follow-on process to the 14nm/16nm node and will provide a choice of either finFET or planar FD-SOI architectures. But the likely absence of EUV will increase costs.
May 19, 2014

14nm/16nm processes

The 14nm and 16nm processes cover a range of technologies and are designed to succeed the 20nm generation. They bring with them a number of design challenges.
April 28, 2014

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
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April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
March 27, 2014
Achieving multi-scenario signoff more quickly and predictably using timing-driven ECO

Achieving multi-scenario signoff quickly and predictably using timing-driven ECO

Using a physically aware flow to ensure that fixing one ECO doesn't introduce another during sign off.
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February 11, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

The new landscape of advanced design

Advanced tools are being applied to established nodes to produce advanced designs for volume markets.
February 6, 2014
Sudhakar Jilla is group marketing director for place & route at Mentor Graphics.

Concurrency tackles MCMM issues head-on

The number of scenarios needed for MCMM timing analysis has skyrocketed. IC implementation calls for a concurrent approach to deal with the issue.
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January 28, 2014
Mark Bollar is a product marketing director at Synopsys overseeing physical implementation.

Are advanced designs only possible at emerging process nodes?

Advanced design isn’t restricted to emerging process nodes any more. Designers are using the latest tools to produce advanced designs on established nodes.
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?

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