IC Implementation

September 1, 2006

A top-level verification methodology including power supply and signal check using mixed-signal simulation

The ‘state-of-the-art’ solution for wireless transceiver RF ICs is single chip CMOS, integrating digital, analog, and RF blocks on a single chip. The architectures involved require new and challenging approaches to verification. To understand these, we first need to look back at the history of the transceiver architectures used for wireless mobile phone implementations during […]

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September 1, 2006

Coverage-driven verification for the analog domain

The verification of digital sub-systems is based on advanced techniques such as constraints capture, randomized or pseudo-randomized stimuli generation and results collection with functional coverage evaluation. The use of manually verified hand-coded analog block models within a digital verification environment has so far been sufficient. However, the move to greater levels of integration, shrinking process […]

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June 1, 2006

I hate to say this but…

Joe Costello The dominant theme for DAC 2006 is multimedia, games and entertainment. So how does Cadence Design Systems founder and former CEO Joe Costello fit into that? He is after all giving the conference’s Monday keynote. Let’s do the ticklist. EDA credentials? Dated – he left Cadence in 1998 – but basically a ‘check’. […]

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June 1, 2006

Back on the bay

Ellen Sentovich As EDA Tech Forum went to press, the programme for 2006’s Design Automation Conference (July 24-28) in San Francisco was only just being made public. However, one thing was already clear. The event is set to be bigger than ever before. “We had been concerned about the move to July because of the […]

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June 1, 2006

Deploying the right tools for mixed signal verification

Engineers on the leading edge of nanometer design are dealing with physical effects that change the way mixed-signal ICs are verified – in timing, power, reliability and yield. With the IC verification effort accounting for 60-80% of the development cycle, choosing and deploying the right mixed-signal verification solution can significantly improve productivity and the return […]

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March 1, 2006

ARM and the man

When microprocessor core developer ARM started in a barn outside Cambridge, England, just over fifteen years ago, odds were against it making a global impact. The team of “12 engineers and me”, as then CEO and now chairman Sir Robin Saxby puts it, “had no patents, a working prototype and £1.75m of cash.” Without the […]

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March 1, 2006

Making the DATE

DATE 06 (March 6-10) is the ninth edition of the Design Automation and Test in Europe conference and the organizers have again received a record number of submissions, this year 834. This reflects the fact that today DATE is not merely a European conference but has become a well-known global event, receiving paper proposals and […]

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March 1, 2006

Which ADC architecture is right for your application – Part Two

Selecting the proper ADC can appear a formidable task. A direct approach is to go to the selection guides and parametric search engines. Enter the sampling rate, resolution, power supply voltage, and other properties. Click ‘find’. But can one approach the task with greater understanding — particularly of the main architectures — and get better […]

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December 1, 2005

Which ADC architecture is right for your application – Part One

Introduction Selecting the proper ADC can appear a formidable task, considering the thousands on the market. A direct approach is to go to the selection guides and parametric search engines. Enter the sampling rate, resolution, power supply voltage, and other properties. Click ‘find’. And hope for the best. But it’s usually not enough. How does […]

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December 1, 2005

A new canonical form for fast Boolean matching in logic synthesis and verification

An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition, an efficient algorithm for computing the proposed canonical form is provided. The efficiency of the algorithm allows it to be applicable to large complex Boolean functions with no limitation on the number of input […]

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