IC Implementation

Finding and fixing double patterning problems in 20nm designs

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design

Current techniques for modelling RF power amplifiers don't provide the dynamic range necessary to simulate their performance properly when used in the energy-saving envelope-tracking mode necessary to give LTE terminals a decent battery life.

Intel says ‘trigate’—finFET to others—but depleted silicon-on-insulator also has its post 22nm supporters. Chris Edwards reports on the debate at 2011’s Semicon West.

We quiz TSMC’s Tom Quan on the latest methodological challenges being addressed by the world’s largest foundry’s signature Reference Flow.

The 28nm process node has once more raised the design bar in terms of the DFM checks needed to realize a design. This is particularly true for analog and mixed-signal engineering, where rules that could once be maintained manually now need to be addressed in a more integrated, automated, and timely way. The article explores [...]

A bid for more interactivity is one of the program cornerstones for the 48th Design Automation Conference.

Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.

DATE 2011 will be held this month around one of France's most active high-tech clusters. We preview some of the conference's highlights.

The article reviews the design assessment process that a company should undertake when developing an analog-centric application-specific integrated circuit (ASIC). The authors argue that a number of myths surround strategies that incorporate a large amount of specialist analog design work, including evaluations related to cost and functionality. In particular, the need for differentiation in today's [...]