ESL

May 15, 2014
Bill Neifert is chief technology officer of Carbon Design Systems. Bill has designed high-performance verification and system integration solutions, and also developed an architecture and coding style for high-performance RTL simulation in C/C++.

Bringing true power analysis to hardware/software co-design

While some HW/SW co-design and verification techniques are in place, a power analysis methodology is only just emerging
December 16, 2013
forte-hsl-2-featim

How high-level synthesis helps optimize low power designs – Part Two

Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
November 14, 2013
Cadence virtual prototyping

A map of the prototyping ecosystem

Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
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November 1, 2013
Jack Erickson is director of product management at Cadence Design Systems.

Slow winter or new spring for hardware design?

Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
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October 21, 2013
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How high-level synthesis helps optimize low power designs – Part One

Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
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April 10, 2013
Richard Goering, senior manager of technical communications, Cadence

Focus on product creation for effective design

An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
January 18, 2013
tdf-jan13-ment-esl-featim

Get more out of system architectures

This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
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November 16, 2012
Synopsys Virtualizer screen shot

The Shift Left: how virtual prototyping reduces risk

The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
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October 26, 2012
velocefeatured

Emulation delivers system-level power verification

Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
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October 25, 2012

Vivado HLS/AutoESL: Agilent packet engine case study

How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine

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