Continuing our series on high-level synthesis (HLS) for low power design. Part Two details how HLS helps you make and evaluate architectural decisions.
Different users within a design team will have varying needs for prototype capabilities. What type of prototype to pick is not always 100 per cent clear. Here are some pointers on how to make the choice.
Problems with process scaling make it seem as though the long era of innovative, lucrative hardware design is coming to an end. But is that really the case?
Going inside HLS' basics shows how it can deliver power savings over 50% for some applications.
An increasingly important concept in design is that of product creation. An approach based on product creation looks beyond chip or board design.
This case study shows how the evaluation of various design options requires a thorough approach to system-level modeling.
The business case behind how virtual prototyping speeds development, improves hardware and software quality, and improves ROI.
Overcome the time and visibility limitations of simulation and of gate-level and RTL-based strategies to achieve full-chip analysis.
How Xilinx' Vivado HLS enabled the creation of an in-fabric, processor-free UDP network packet engine
The FPGA vendor's new flagship is now on public release. It adds an array of features, including support for system-level to HDL synthesis.
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