October 19, 2011

Plan for 450mm or pay the price

The launch of a broad-based IDM/foundry consortium that is to prepare for the shift to 450mm wafers already offers some hints as to the future shape of chip manufacturing and the planning demands it will impose on all design managers in the near future. The game is shifting from pay-for-capacity to outright pay-to-play for those [...]
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August 25, 2011

Selective CVD growth of germanium-tin: a new approach for implementing stress in germanium-based MOSFETs

Belgian research institute Imec describes, for the first time, the selective chemical vapor deposition (CVD) of germanium-tin (GeSn) in a production-like environment using commercially available Ge and Sn precursors. The resulting GeSn layers with 8% Sn are defect free, fully strained and thermally stable for temperatures up to 500°C. The technique is used to implement [...]
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August 23, 2011

Quantifying returns on litho-friendly design

By the time a serious lithography-related problem is identified at the fab, it is too late in the design process to make simple layout changes. To avoid or reduce design delays, Infineon Technologies uses lithography simulation to detect weak points in a layout and analyze the effect of lithography on the design’s electrical performance. Its [...]
June 20, 2011

Foundry overcapacity – yes, it could happen

Current shortages could switch in key markets by the end of the year.
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June 2, 2011

DRC+: a pattern-based approach to physical verification

DRC+ is a new methodology that algorithmically characterizes design variation through pattern classification. A traditional design rule is used to identify all design structures that share a common configuration. Then, the 2D geometric situations (pattern variations) around the configuration are extracted and classified. Since all such classes share a common configuration, each situation class represents [...]
June 1, 2011

Balancing devices and manufacturing

Fab owners are looking to bring down their energy consumption to match the greening of semiconductors themselves.
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June 1, 2011

SRAF Enhancement using Inverse Lithography for 32 nm Hole Patterning and Beyond

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC […]

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June 1, 2011

Automated DRC Waiver Management (or, How I Learned to Stop Worrying About IP Waivers and Love Calibre Auto-Waiver)

This paper explains the Calibre Auto-Waiver product, and discusses how the auto-waiver process significantly reduces the time and risks associated with implementing third-party IP. Integration of third-party intellectual property (IP) into integrated circuit (IC) designs has always been a potential time trap for IC designers. IP design rule violations that were waived by the foundry […]

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June 1, 2011

An Innovative Method to Automate the Waiver of IP-Level DRC Violations

Intellectual property (IP) blocks often contain known design rule checking errors that have been “waived” by the foundry, meaning they acknowledge the error as a design rule violation, but do not consider it to be a critical yield-limiting defect. Because this waiver information is not conveyed in any consistent manner with the IP, waived IP […]

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June 1, 2011

The Evolution of Patterning Process Models in Computational Lithography

Thirty five years have passed since the first lithography process models were presented, and since that time there has been remarkable progress in the predictive power, performance, and applicability of these models in addressing many different challenges within the semiconductor industry. The impact has been profound, and this paper will attempt to highlight some of […]

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