DFM

September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
August 30, 2017
DTCO for early lithography issue identification - featured image

Your next node: find lithography issues early with DTCO

Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
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May 8, 2017
Dr Walden Rhines is Chairman and CEO of Mentor - A Siemens Business

The Wally Rhines interview – Part One: Mentor as a Siemens business

Our extended fireside chat with Mentor Chairman and CEO Wally Rhines begins by canvassing his thoughts now the Siemens deal is done.
March 22, 2017
Computational Process Control feature

How Applied Materials and fab partners are harnessing machine learning

The equipment giant's Computational Process Control strategy takes a pragmatic approach to Industry 4.0 and is likely to influence EDA tools for incoming nodes.
October 3, 2016
Place and route beyond 10nm

How place and route is adapting to challenges below 10nm

Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
September 23, 2015

Mounting Fiji: How AMD realized the first volume interposer

AMD's Radeon R9 family is the result of eight years developing 3D-IC and interposer technology. What lessons did the company learn?
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March 26, 2015

A review of model development for 10nm lithography

John Sturtevant looks at ongoing preparations for the incoming node and charts significant progress that has already been made.
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January 26, 2015
Silicon Photonics litho featured image

How lithography simulations enable silicon photonics

Precise curved geometries are vital to making this emerging and cost-effective CMOS-based technology work. This primer explains its advantages and how litho tools are evolving to meet the challenges it presents.
November 5, 2014
Pattern matching DRC featured image

How to use pattern matching to improve automatic waiver management

Fab and IP vendor collaboration is making pattern matching-based libraries a vital component of DRC accuracy and efficiency. Learn how to take advantage.
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October 10, 2014
Dr Yervant Zorian, Synopsys

Finding and fixing faults in finFET memories

FInFET memories have different defects than those based on planar transistors. Here's how to test and repair them.
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