DFM

April 10, 2013
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
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April 1, 2013

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
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December 4, 2012
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
December 3, 2012

Overcoming dummy fill deck limitations for analog design

CSR used a customized approach to automated dummy fill layout for AMS to address layer density and device matching issues in standard flows aimed at digital SoCs.
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October 11, 2012
Tong Gao

The physical design challenges of 20nm processes

Manufacturability, routing, library design and more - it all needs rethinking at 20nm, writes Tong Gao of Synopsys.
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October 9, 2012

Physical verification of 20nm designs through integrated double-patterning analysis and repair

Finding and fixing double patterning problems in 20nm designs
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September 12, 2012

Critical tools for 20nm design

A look at the way in which key tools, in IC implementation, modeling and extraction, and physical verification, are developing in response to the challenges of 20nm design
September 6, 2012
Antun Domic

Getting ready for 20nm

Antun Domic of Synopsys tackles the three key challenges of 20nm processes: design complexity; the physics of lithography; and economics.
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August 21, 2012

2.5D-IC, 3D-IC, and 5.5D-IC – stacked-die integration

A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.
July 26, 2012
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Optimizing cloud computing for faster semiconductor design

How Cadence, Intel and Xuropa accelerated the semiconductor design process by squeezing 15% more capacity out of a virtualized server farm
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