DFM

December 9, 2013
Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.

FinFET parasitics come under control

Extracting finFET parasitics means a shift to 3D models, field solvers for greater accuracy, and MCMM techniques.
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December 3, 2013
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

Lithography challenges threaten the cost benefits of IC scaling

The costs of advanced lithography techniques at 1xnm, and the yield and reliability risks from the resultant process variation, will stop many companies getting the typical economic advantages of scaling.
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October 11, 2013
Mentor Power Grid article featured image

Power grid analysis for 2.5D and 3D IC systems

PGA has been IC-centric for mainstream 2D configurations. It must become system-centric for 2.5D and 3D systems.
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October 8, 2013
Cadence EAD flow

End mixed-signal infinite loops with electrically aware design

Electrically aware layout tools provide a more efficient alternative to time-consuming rip-up-and-retry practices in mixed-signal nanometer IC design.
October 2, 2013
tdf-ment-lde-featim

Catching layout-dependent effects on-the-fly

New layout-dependent effects (LDEs) arise at each process node. This methodology updates LDE parameters and uses on-the-fly simulation for early detection.
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May 8, 2013
3D-IC cross-section

Eight requirements for 3D-IC design

Many design teams are looking at ways in which they can make use of 3D integration. Here are eight requirements for an effective 3D-IC design flow.
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April 22, 2013
Layout segment showing problem of color splitting with double patterning

The five key challenges of sub-28nm custom and analog design

The arrival of the 20nm and finFET-based 14nm and 16nm processes bring with them challenges for custom IC design. These are the five key areas and a methodology that can address them.
April 10, 2013
Marco Casale-Rossi is a senior staff product marketing manager in the Design Group at Synopsys.

Time to take up the 3D integration challenge

It’s time to take up the challenge of applying 3D integration technology to IC design. The manufacturing process technology is maturing, the tool chains are in place, and the opportunities to broaden your market by applying a new form of systemic integration are growing.
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April 1, 2013
tdf-ment-waivers-fig1-featim

Improving SoC productivity through automatic design rule waiver processing for legacy IP

You can waive some physical verification errors related to legacy IP found in foundry DRC checks. Knowing which has involved lengthy manual analysis. TSMC is enhancing the process with automation.
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December 4, 2012
Dr David M Fried is Chief Technology Officer - Semiconductor at Coventor, responsible for the company’s strategic direction and implementation of its SEMulator3D Virtual Fabrication Platform.

FinFET tipsheet for IEDM

finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?

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