DFM

June 30, 2014
Future of thermal simulation

The future of thermal simulation for electronics products

Complexity and the increasing use of thermal analysis software by non-expert designers demands new approaches for chip and PCB implementations.
June 18, 2014
Parasitic Extraction Featured Image

Full 3D-IC parasitic extraction

How to enhance an 'ideal' parastitic extraction strategy to create a full 3D assembly-level parasitic netlist for simulation and circuit analysis.
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May 30, 2014
propfeatim

How the right DFY flow enhances performance and profit

'Design for yield' is a familiar term, but the challenges in today's increasingly large projects make a refresher on what it offers particularly timely.
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May 26, 2014
Unidirectionally routed M1 using SADP (Source: CMU/IBM)

Triple patterning and self-aligned double patterning (SADP)

In the absence of EUV lithography, the primary option for manufacturing on a 10nm process is to extend double patterning. But the options each have issues.
April 28, 2014
John Ferguson is the director of marketing for Calibre DRC applications at Mentor Graphics. John has worked extensively in the area of physical design verification for the manufacture of leading edge integrated circuits.

Protecting IP in a collaborative signoff environment

The encryption chain for today's highly collaborative designs needs to be managed with care.
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April 3, 2014
Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics.

Standard cell IP must pass the litho-friendly routing test

Lithography is only just beginning to play a role in cell IP selection but early analysis already matters.
January 20, 2014
Jean-Marie Brunet is the Product Marketing Director for DFM at Mentor Graphics

Patterning choices loom for 10nm and beyond

It is not just a choice between EUV and multiple patterning for future nodes, but even between varieties of multi-mask technologies. How will you decide?
January 13, 2014
Interconnect resistance has increased since the 40nm node

Interconnect resistance

A number of effects have led to a dramatic increase in interconnect resistance in the sub-32nm process nodes that demands the use of smarter routing.
January 13, 2014
Multiple patterning is causing issues with access to standard-cell pins in nanometer processes

Cell pin access

Increasingly complex design rules in 14nm and 16nm make it harder to connect local routing to the inputs and outputs (pins) of standard cells.
January 13, 2014
Steffen Schulze is director of marketing for Calibre Mask Data Preparation at Mentor Graphics

Consider your options for future nodes

If EUV is further delayed until 8nm, the industry has to explore other options for patterning, and the effects they will have on the DFM flow.

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