A major issue faced by SoC design teams adopting 90nm and 65nm process nodes is the increase in yield fall-out. At 90nm it is estimated that 30% of yield fall-out is due to performance and signal integrity issues. As a result, accurate and cost effective at-speed manufacturing test and characterization has become evermore critical to […]
Leakage has become a critical concern for sub-100nm silicon process technologies. It had started to become a significant factor in a chip’s overall power profile at 130nm, but by 90nm things had worsened with leakage accounting for perhaps 30% of a chip’s total power consumption. At 65nm, leakage represents more than 50% of power consumption. […]
The most expensive parts of today’s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is […]
More than 50% of highly complex systems-on-chip (SoCs) have functional issues at first silicon, issues that emerge after engineers have spent much time and money on verification and emulation. These issues delay time-to-ramp and cause significant losses of direct and indirect product revenue. All this demonstrates the need for efficient post-silicon debug methodologies and tools. […]
Analyses made by semiconductor manufacturers have demonstrated that maintaining pattern fidelity is critical, and that this task faces increasing limitations at the 65nm process node and below. At these technology nodes, even the most advanced resolution enhancement technologies (RET) have a difficult time with certain layout topologies. When the impact of this is observed across […]
Kerry Bernstein When Kerry Bernstein, a 28-year IBM veteran, was first drafted to work on Big Blue’s development of 3D semiconductors, he admits he was a skeptic. “At first, I think I felt as though I’d got dragged into this program. I thought it wasn’t going anywhere. I thought it was going to go anywhere. […]
Design-for-manufacturability (DFM) has become pervasive and there is general agreement on the need to apply DFM at multiple stages of the design cycle. DFM techniques at the relatively mature 0.13um technology node entail well known enhancements such as contact and via redundancy, line-ends and borders, and wire spreading. Mature technology nodes achieve product yields which, […]
Introduction As semiconductor manufacturing moves into the sub-100nm realm, the need for increased cooperation and communication between design and manufacturing becomes more apparent. Manufacturing is becoming increasingly complex, and many of the principles that have guided design and manufacturing no longer apply. Some of the major changes occurring in wafer manufacturing include: The industry is […]
So far, the debate over design for manufacturing (DFM) has featured contributions from, principally, four groups: designers, manufacturers, EDA vendors and the consultancy community. It is becoming increasingly apparent that some other voices need to be heard and their positions integrated within any successful semiconductor DFM chain. One such group is fab equipment suppliers. The […]
Nanometer scaling severely inhibits the path to achieve sustainable yield. In response more responsibility for forecasting potential failures must shift to design for manufacturing (DFM) methodologies that can be applied early in the design process. Yet, while these hold much promise, manufacturing test and failure analysis remains at the forefront of determining why chips fail. […]
