DFM

April 23, 2018
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The three critical data validation points in a design flow

Why design data integrity matters from cell design to tapeout. These techniques will help ensure your validation process is as comprehensive as possible.
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April 17, 2018
Guido Groeseneken is an Imec fellow, researching advanced devices and the reliability physics of sub-10nm CMOS technologies.

Reliability research helps to create new technologies

Insights from research into reliability at Imec led to self-learning chips, security technologies, and finFET biosensors.
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March 29, 2018
Two wafers fabbed at Imec

3DIC technology provides performance boosts

3D integration technology has split into a number of different approaches, each of which brings a different combination of benefits in terms of performance.
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February 1, 2018
Design space exploration feature

Design space exploration finds hotspots during early process development

A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.
January 15, 2018
Physical Verification Efficiencies - featured image

Three ways to lift productivity during physical verification

How to get the best PV results by reducing computational demands; handling data more efficiently and exploiting parallelization.
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November 24, 2017
John Ferguson is the Director of Marketing for Calibre DRC Applications at Mentor, a Siemens Business, in Wilsonville, Oregon, with extensive experience in physical design verification. He holds a BS degree in Physics from McGill University, an MS in Applied Physics from the University of Massachusetts, and a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology.

Assessing the true cost of node transitions

John Ferguson reviews the key capital metrics you need to review when deciding whether to move to a new process.
October 27, 2017
Featured image - double patterning at advanced nodes

Catch multi-patterning errors clearly at advanced nodes

How to address increasingly complex patterning issues and debug them efficiently as design moves toward 12 and 10nm.
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September 21, 2017
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Yield is money – and other truths of diagnosis-driven yield analysis

Diagnosis-driven yield analysis identifies the cause of systematic yield loss to speed the ramp-to-volume on new processes and improve yield on mature ones.
September 14, 2017
Featured image - Silicon photonics

Silicon photonics moves out of the shadows

An alphabet soup of AI, HPC, 5G and the IoT has finally seeded creation of a design infrastructure for silicon photonics.
August 30, 2017
DTCO for early lithography issue identification - featured image

Your next node: find lithography issues early with DTCO

Pattern-based design/technology co-optimization (DTCO) estimates lithographic difficulty during the early stages of a new process technology node.
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